发明授权
- 专利标题: Method of manufacturing isolated semiconductor devices
- 专利标题(中): 制造隔离半导体器件的方法
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申请号: US758962申请日: 1985-07-25
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公开(公告)号: US4685198A公开(公告)日: 1987-08-11
- 发明人: Kenji Kawakita , Noboru Nomura , Toyoki Takemoto
- 申请人: Kenji Kawakita , Noboru Nomura , Toyoki Takemoto
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 主分类号: H01L21/762
- IPC分类号: H01L21/762 ; H01L21/763 ; H01L29/06
摘要:
Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.