发明授权
- 专利标题: Transistor circuit for signal multiplier
- 专利标题(中): 用于信号倍增器的晶体管电路
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申请号: US706597申请日: 1985-02-28
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公开(公告)号: US4694204A公开(公告)日: 1987-09-15
- 发明人: Kazunori Nishijima , Mitsutoshi Sugawara
- 申请人: Kazunori Nishijima , Mitsutoshi Sugawara
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX59-38010 19840229; JPX59-164434 19840806
- 主分类号: G06G7/163
- IPC分类号: G06G7/163 ; H03L7/087 ; H04L27/00 ; H04L27/227 ; H03B17/00 ; G06G7/16
摘要:
A transistor circuit for a signal multiplier used in, for example, a demodulator by means of the Costas loop method is disclosed. The transistor circuit comprises first to third circuit stages each including first and second transistors coupled in a differential form. The first to third circuit stages are connected in tandem with one another such that the output signal current of each circuit stage is supplied to the succeeding circuit stage without a substantial change. Further, each of the first to third circuit stages is supplied with one of or both of two input signals P and Q. As a result, the transistor circuit produces an output signal representing a signal multiplication: P.times.Q.times.(P+Q).times.(P-Q).
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