An amorphous semiconductor device comprising a layered structure having a p-amorphous silicon layer, an i-amorphous silicon layer, an n-amorphous silicon layer, an i-amorphous silicon layer and a p-amorphous silicon layer, or an n-amorphous silicon layer, an i-amorphous silicon layer, a p-amorphous silicon layer, an i-amorphous silicon layer and an n-amorphous silicon layer, in sequence, on a substrate, electrodes being disposed on the top layer, the central layer and the bottom layer, respectively.