A method for the simulation of an error in a logic circuit which comprises a bus optionally connectible to different logic levels, utilizes the assistance of input bit patterns from which output bit patterns are derived via a simulation model containing the error, these output bit patterns being compared to reference bit patterns which are valid for error-free operation. The object is a reliable recognition of an error which leads to a bus conflict, by applying different logic levels to the same circuit mode, by way of an output bit pattern which deviates from a reference bit pattern. This is achieved in that the bus, including the switch elements connecting the levels, is modeled by gate functions, whereby the undefined bus level given simultaneous connection of different logical levels is imaged into a logical "0" by a first bus model version and is imaged into a "1" by a second bus model version. Both bus model versions are respectively utilized in one segment of the simulation method.