发明授权
- 专利标题： Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom
- 专利标题（中）： 栅电极制造方法和由其制成的对称和非对称自对准嵌体晶体管
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申请号： US840635申请日： 1986-03-17
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公开(公告)号： US4737828A公开(公告)日： 1988-04-12
- 发明人: Dale M. Brown
- 申请人： Dale M. Brown
- 申请人地址： NY Schenectady
- 专利权人： General Electric Company
- 当前专利权人： General Electric Company
- 当前专利权人地址： NY Schenectady
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/336 ; H01L29/78 ; B44C1/22 ; C23F1/02 ; H01L21/00 ; H01L21/306
摘要：
An edge defining method is employed in the fabrication of narrow electrical patterns for VLSI circuits. The method is particularly employable in the formation of inlay MOSFET transistors having extremely narrow gate widths. The method is also particularly amenable to the fabrication of both symmetrical and non-symmetrical MOSFET devices on the same VLSI circuit chip. The inlay transistor structure is also employed to fabricate NOR and NAND type "ladder" networks and to join vertically and horizontally adjacent semiconductor devices.
公开/授权文献
- US5896879A Flow damper for a cleaning station 公开/授权日：1999-04-27
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