The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.