公开(公告)号：US4755938A

公开(公告)日：1988-07-05

申请号：US920946

申请日：1986-10-20

申请人： Masanori Takahashi ,  Hidehiko Nishida ,  Minoru Koshino ,  Akira Hattori

发明人： Masanori Takahashi ,  Hidehiko Nishida ,  Minoru Koshino ,  Akira Hattori

IPC分类号： G06F12/00 ,  G06F9/48 ,  G06F13/12 ,  G06F13/18 ,  G06F9/38

CPC分类号： G06F13/18

摘要： The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.

摘要翻译： 本发明涉及一种访问请求控制装置，更具体地涉及一种用于确定使用流水线的存储器控​​制装置中的多个访问请求之间的优先级的装置。 来自多个信道处理设备CHP的接入请求之一由第一优先级确定电路选择。 所选择的CHP请求，来自多个中央处理单元的请求和流水线控制电路的环回请求被考虑用于由第二优先级确定电路进行选择。 在由第一优先级确定电路选择的CHP请求不被第二优先级确定电路选择或者在流水线中被选择但无效的情况下，CHP请求返回到第一优先级确定电路。 但是，在这种情况下，在第一优先级确定电路中对CHP请求赋予较高的优先级。 此外，第二优先级确定电路中的优先级算法考虑到每个访问请求的操作的种类，并且可以实现高效的存储器访问控制。

公开(公告)号：US4547848A

公开(公告)日：1985-10-15

申请号：US509869

申请日：1983-06-30

申请人： Hidehiko Nishida ,  Minoru Koshino ,  Terutaka Tateishi ,  Akira Hattori

发明人： Hidehiko Nishida ,  Minoru Koshino ,  Terutaka Tateishi ,  Akira Hattori

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F13/00

CPC分类号： G06F13/18

摘要： This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access requesting unit in parallel with the access to MS by the first access request.

摘要翻译： 本发明涉及一种用于处理从多个访问请求单元向存储器发出的访问请求的系统。 特别地，在提供缓冲存储BS和主存储MS的存储系统中，首先基于和访问请求对BS进行访问，并且如果在BS中没有找到所需的数据，则对MS进行访问。 当在BS中没有找到期望的数据，然后对MS进行访问时，基于来自同一访问请求单元的下一个访问请求，与通过第一访问请求访问MS并行地执行对BS的访问。

公开(公告)号：US5555560A

公开(公告)日：1996-09-10

申请号：US452576

申请日：1995-05-25

申请人： Hiroshi Komatsuda ,  Hidehiko Nishida

发明人： Hiroshi Komatsuda ,  Hidehiko Nishida

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1631

摘要： A request cancel system is incorporated in a processing system which includes a main storage unit having a plurality of banks, a memory control unit and a plurality of access units, such as central processing units (CPUs), which access the banks of the main storage unit via the memory control unit. A check part in the request cancel system detects whether or not a bank designated by an address of an access request from one of the access units is in use by reading a corresponding bank busy flag from a bank busy flag group. After the check part has determined that a bank designated by an address of a first access request is not busy, a flag is sent to the bank busy flag group to indicate that the bank accessed by the first access request is busy. A second access request to the bank accessed by the first access request can be processed by the check part before the flag is set in the bank busy flag group. A comparator compares the addresses of the first access and second access requests and outputs a coincidence signal when the addresses of the first and second access requests coincide. A request cancel controller cancels the second access request in response to the coincidence signal from the comparator.

摘要翻译： 请求取消系统被并入处理系统中，该处理系统包括具有多个存储体的主存储单元，存储器控制单元和多个访问单元（诸如中央处理单元（CPU）），其访问主存储器 单元通过存储器控制单元。 请求取消系统中的检查部分通过从银行忙标志组读取相应的银行忙碌标志来检测来自其中一个访问单元的访问请求的地址指定的存储体是否在使用。 在支票部分确定由第一访问请求的地址指定的银行不忙时，将标志发送到银行忙标志组，以指示由第一访问请求访问的银行正忙。 通过第一访问请求访问的银行的第二访问请求可以在标志被设置在银行忙标志组之前由检查部件处理。 比较器比较第一接入请求和第二接入请求的地址，并且当第一和第二接入请求的地址一致时输出一致信号。 响应于来自比较器的一致信号，请求取消控制器取消第二访问请求。

公开(公告)号：US5218688A

公开(公告)日：1993-06-08

申请号：US794844

申请日：1991-11-21

申请人： Hidehiko Nishida

发明人： Hidehiko Nishida

IPC分类号： G06F13/18

CPC分类号： G06F13/18

摘要： In a data processing system including a plurality of multi-processor systems, each multi-processor system having at least one central processing unit and at least one main memory both connected to a memory control unit, each memory control unit is connected to each other memory control unit, the memory control unit comprises plural ports, plural registers, access selection circuits for innner and outer access, a priority control circuit, a first and a second control circuit, and wait signal reset circuit, a priority of accesses from the same central processing unit to the other multi-processor system is detected, and the registers to store the access request signals in the other multi-processor system are efficiently used by adding a priority control signal to the access request signal. Thus, the data throughput of the system and the speed of the access are improved.

摘要翻译： 在包括多个多处理器系统的数据处理系统中，每个多处理器系统具有连接到存储器控制单元的至少一个中央处理单元和至少一个主存储器，每个存储器控制单元连接到彼此的存储器 控制单元，存储器控制单元包括多个端口，多个寄存器，用于内部和外部访问的访问选择电路，优先级控制电路，第一和第二控制电路以及等待信号复位电路，来自相同中央的访问的优先级 检测到处理单元到另一个多处理器系统，并且通过向访问请求信号添加优先级控制信号来有效地使用用于存储另一多处理器系统中的访问请求信号的寄存器。 因此，提高了系统的数据吞吐量和访问速度。

公开(公告)号：US4718006A

公开(公告)日：1988-01-05

申请号：US682316

申请日：1984-12-17

申请人： Hidehiko Nishida

发明人： Hidehiko Nishida

IPC分类号： G06F13/00 ,  G06F13/16

CPC分类号： G06F13/1657

摘要： A data processor system includes a plurality of multiprocessor systems, and each multiprocessor system is connected through each memory control unit of each multiprocessor system. Each multiprocessor system comprises a memory control unit, at least one central processing unit, at least one channel control unit, and at least one main memory unit. The central processing unit, channel control unit, and main memory unit are connected to the memory control unit via interface lines. The memory control unit comprises at least two pipelines and at least two access requests to the main memory unit belonging to the pipe-line, and the other pipe-line is used for access requests to another main memory unit belonging to another memory control unit.

摘要翻译： 数据处理器系统包括多个多处理器系统，并且每个多处理器系统通过每个多处理器系统的每个存储器控制单元连接。 每个多处理器系统包括存储器控制单元，至少一个中央处理单元，至少一个通道控制单元和至少一个主存储器单元。 中央处理单元，通道控制单元和主存储单元经由接口线连接到存储器控制单元。 存储器控制单元包括属于管线的至少两条管线和至少两条对主存储器单元的访问请求，另一条管线用于对属于另一存储器控制单元的另一主存储器单元的访问请求。