发明授权
US4819212A Nonvolatile semiconductor memory device with readout test circuitry
失效
具有读出测试电路的非易失性半导体存储器件
- 专利标题: Nonvolatile semiconductor memory device with readout test circuitry
- 专利标题(中): 具有读出测试电路的非易失性半导体存储器件
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申请号: US50717申请日: 1987-05-18
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公开(公告)号: US4819212A公开(公告)日: 1989-04-04
- 发明人: Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
- 申请人: Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX61-126359 19860531; JPX61-157299 19860704
- 主分类号: G11C8/12
- IPC分类号: G11C8/12 ; G11C16/08 ; G11C7/00 ; G11C7/02 ; G11C8/00
摘要:
A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.
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