An I/O controller for a computer system having a plurality of memory devices of different types such as floppy and hard disks, whereinn a single cache memory is employed for all of the memory devices. Each of the memory devices is provided with its own interface device which directs data outputted from the associated memory device onto a common device bus. From the device bus data is transferred to a cache memory via a separate cache bus, and then to a system processor via the same cache bus. Memory space within the cache memory may be allocated among the various memory devices.