发明授权
US4829014A Screenable power chip mosaics, a method for fabricating large power
semiconductor chips
失效
可屏蔽电源芯片马赛克,一种制造大功率半导体芯片的方法
- 专利标题: Screenable power chip mosaics, a method for fabricating large power semiconductor chips
- 专利标题(中): 可屏蔽电源芯片马赛克,一种制造大功率半导体芯片的方法
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申请号: US189254申请日: 1988-05-02
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公开(公告)号: US4829014A公开(公告)日: 1989-05-09
- 发明人: Alexander J. Yerman
- 申请人: Alexander J. Yerman
- 申请人地址: NY Schenectady
- 专利权人: General Electric Company
- 当前专利权人: General Electric Company
- 当前专利权人地址: NY Schenectady
- 主分类号: G01R31/26
- IPC分类号: G01R31/26 ; H01L21/66 ; H01L21/768 ; H01L21/82
摘要:
An additive process allowing discretionary interconnection of only the acceptable devices on a semiconductor wafer includes screen printing a polyimide layer over the wafer to form vias over all of the device contact pads on the wafer while coating the remainder of the wafer. The devices are then individually tested through the vias and, when a device is determined to be unacceptable according to predetermined specifications, the vias above that device are filled with polyimide. A layer of metal is next deposited over the entire wafer by evaporation and makes electrical contact with only the acceptable devices since the unacceptable devices have been blocked off. The metal layer is thereafter patterned to leave an interconnection pattern wherein only the acceptable devices on the wafer are electrically connected.
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