发明授权
- 专利标题: Nonvolatile semiconductor memory device
- 专利标题(中): 非易失性半导体存储器件
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申请号: US68521申请日: 1987-07-01
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公开(公告)号: US4831592A公开(公告)日: 1989-05-16
- 发明人: Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
- 申请人: Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX61-159742 19860709; JPX61-159744 19860709
- 主分类号: G11C16/30
- IPC分类号: G11C16/30 ; G11C16/32
摘要:
A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.
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