发明授权
- 专利标题: Nonvolatile semiconductor memory device with a bias circuit
- 专利标题(中): 具有偏置电路的非易失性半导体存储器件
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申请号: US235780申请日: 1988-08-23
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公开(公告)号: US4843594A公开(公告)日: 1989-06-27
- 发明人: Sumio Tanaka , Shigeru Atsumi
- 申请人: Sumio Tanaka , Shigeru Atsumi
- 申请人地址: JPX Kawaski
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawaski
- 优先权: JPX60-170021 19850801
- 主分类号: G11C17/00
- IPC分类号: G11C17/00 ; G11C16/06 ; G11C16/22 ; G11C16/24
摘要:
A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.
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