公开(公告)号：US20080285327A1

公开(公告)日：2008-11-20

申请号：US11934399

申请日：2007-11-02

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22 ,  G11C11/401

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US06671200B2

公开(公告)日：2003-12-30

申请号：US10372886

申请日：2003-02-26

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值 在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US6046926A

公开(公告)日：2000-04-04

申请号：US170104

申请日：1998-10-13

申请人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

发明人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

IPC分类号： G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C14/00 ,  G11C29/12 ,  G11C29/34 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/34

摘要： A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.

摘要翻译： 铁电存储器具有通过开关晶体管连接到位线的存储单元筛选测试电路。 在筛选中，选择至少一个字线，并且数据被同时写入连接到该字线的所有存储器单元中。 由于重写后数据未恢复，因此可以在相同条件下对所有FRAM单元进行屏蔽。 通过该电路，屏蔽具有根据铁电存储器固有的印记特性的写入故障的存储单元。

公开(公告)号：US6002354A

公开(公告)日：1999-12-14

申请号：US166571

申请日：1998-10-06

申请人： Yasuo Itoh ,  Sumio Tanaka

发明人： Yasuo Itoh ,  Sumio Tanaka

IPC分类号： G11C16/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/76 ,  H03M1/78 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/785 ,  H03M1/76

摘要： A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

摘要翻译： 可变电位发生电路包括电阻分压器电路和第一和第二运算放大器。 电阻分压器电路包括在电源节点和接地节点之间串联连接的开关元件和电流调节型数字/模拟转换器电路。 电阻分压器电路具有第一节点，在该第一节点处出现通过对从可变电位输出节点输出的可变电位的电阻划分获得的分压电位和施加虚拟电位的第二节点。 第一运算放大器将第一节点的分压电位与参考电位进行比较，以实现用于设置等于参考电位的可变输出电位的反馈控制。 第二运算放大器将第二节点的虚拟电位与参考电位进行比较，以实现用于设置虚拟电位等于参考电位的反馈控制。

公开(公告)号：US5559737A

公开(公告)日：1996-09-24

申请号：US338827

申请日：1994-11-10

申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C7/12 ,  G11C16/28

摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

摘要翻译： 在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管， 主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件 以及用于均衡感测线和虚拟细胞感测线的条件。 因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

公开(公告)号：US5438542A

公开(公告)日：1995-08-01

申请号：US332493

申请日：1994-10-31

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L27/02

CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

公开(公告)号：US5388084A

公开(公告)日：1995-02-07

申请号：US128087

申请日：1993-09-29

申请人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

发明人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C16/30

摘要： Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

摘要翻译： 公开了一种半导体集成电路装置，其包括用于升压源极电压的升压电路，具有连接到升压电路的输出端子的一端的限压器，用于将升压电路的输出电压限制在给定值，以及 连接到限压器的另一端的电压设定电路，用于任意地调节限压器另一端的电压。 该设计可以将升压电路的输出电压保持在恒定电平，并可将该输出电压设置为任意电压。

公开(公告)号：US5296801A

公开(公告)日：1994-03-22

申请号：US921098

申请日：1992-07-29

申请人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Masao Kuriyama

发明人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Masao Kuriyama

IPC分类号： G11C16/30 ,  G05F3/16

CPC分类号： G11C16/30

摘要： A bias voltage generating circuit supplies a bias voltage to a memory's bit lines. One end of a first transistor is connected to a first power supply. The first transistor conducts in response to a control signal. A second transistor is connected to another end of the first transistor. Another end of the second transistor and a gate of the second transistor are connected to an output node. One end of a third transistor and a gate connected to the output node. One end of a fourth transistor and a gate are connected to a second end of the third transistor. A second end of the fourth transistor is connected to a second power supply. One end of a fifth transistor is connected to the first power supply. The fifth transistor also conducts in response to the control signal. A sixth transistor is connected to a second end of the fifth transistor. A second end of the sixth transistor is connected to the output node and the gate of the sixth transistor is connected to a potential source. A seventh transistor is connected to the output node. A second end of the seventh transistor is connected to a ground potential. The seventh transistor also conducts in response to the control signal. The output node outputs a bias voltage to the bit lines when the control signal is activated, and is grounded through the seventh transistor when the control signal is non-activated.

摘要翻译： 偏置电压产生电路将偏置电压提供给存储器的位线。 第一晶体管的一端连接到第一电源。 第一晶体管响应于控制信号而导通。 第二晶体管连接到第一晶体管的另一端。 第二晶体管的另一端和第二晶体管的栅极连接到输出节点。 第三晶体管的一端和连接到输出节点的栅极。 第四晶体管和栅极的一端连接到第三晶体管的第二端。 第四晶体管的第二端连接到第二电源。 第五晶体管的一端连接到第一电源。 第五晶体管也响应于控制信号而导通。 第六晶体管连接到第五晶体管的第二端。 第六晶体管的第二端连接到输出节点，第六晶体管的栅极连接到电位源。 第七晶体管连接到输出节点。 第七晶体管的第二端连接到地电位。 第七晶体管也响应于控制信号而导通。 当控制信号被激活时，输出节点向位线输出偏置电压，并且当控制信号不被激活时，输出节点通过第七晶体管接地。

公开(公告)号：US5233566A

公开(公告)日：1993-08-03

申请号：US614140

申请日：1990-11-16

申请人： Keniti Imamiya ,  Shigeru Atsumi ,  Sumio Tanaka

发明人： Keniti Imamiya ,  Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/82 ,  H01L27/10

CPC分类号： G11C29/789 ,  G11C29/24

摘要： An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.

摘要翻译： 提供冗余存储单元的地址检测器，其包括用于存储用于用冗余单元替换有缺陷单元的地址数据的编程元件。 在测试模式中，冗余单元可被写入，而不管存储单元是否有缺陷。 因此，可以对冗余单元进行测试，而不需要用冗余单元代替缺陷单元的编程元件。 检测器还包括用于锁存编程元件的状态的锁存器和用于在测试模式下设置锁存器的数据设置元件。

公开(公告)号：US5105385A

公开(公告)日：1992-04-14

申请号：US703704

申请日：1991-05-21

申请人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

发明人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

IPC分类号： H01L21/8247 ,  G11C7/14 ,  G11C16/28 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column. A dummy bit line is connected to the dummy capacitance cells and dummy memory cell, and a dummy word line is connected to the array edge memory cell and dummy memory cell.