This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.