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发明授权
US4916665A Semiconductor memory device with P-channel MOS transistor load circuit 失效
具有P沟道MOS晶体管负载电路的半导体存储器件

Semiconductor memory device with P-channel MOS transistor load circuit
摘要：
A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.
摘要（中）：

本发明的半导体存储器件具有多个浮动栅极存储单元。 检测器检测由解码器选择的存储在浮动栅极存储单元中的数据，并产生相应的检测信号。 负载电路放大检测信号。 放大的检测信号被提供给差分放大器。 差分放大器将放大的检测信号的电压与参考电压发生器的参考电压进行比较，并产生与浮动栅极存储器中的存储内容相对应的二进制信号。 负载电路是p沟道增强型MOS晶体管。 负载晶体管具有栅极和漏极，其连接到检​​测器和差分放大器之间的节点，并且还具有接收预定电压的源极和衬底。

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