发明授权
US4918692A Automated error detection for multiple block memory array chip and
correction thereof
失效
多块存储器阵列芯片的自动错误检测及其校正
- 专利标题： Automated error detection for multiple block memory array chip and correction thereof
- 专利标题（中）： 多块存储器阵列芯片的自动错误检测及其校正
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申请号： US201413申请日： 1988-06-02
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公开(公告)号： US4918692A公开(公告)日： 1990-04-17
- 发明人: Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
- 申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX62-139174 19870603
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G06F11/10 ; G11C11/401 ; G11C29/04 ; G11C29/42 ; H01L27/10
摘要：
A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.
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