发明授权
- 专利标题: Semiconductor memory device having sub bit lines
- 专利标题(中): 具有子位线的半导体存储器件
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申请号: US182895申请日: 1988-04-18
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公开(公告)号: US4920517A公开(公告)日: 1990-04-24
- 发明人: Hiroyuki Yamauchi , Toshio Yamada , Michihiro Inoue
- 申请人: Hiroyuki Yamauchi , Toshio Yamada , Michihiro Inoue
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX61-95364 19860424; JPX62-93604 19870416; JPX62-164544 19870701
- 主分类号: G11C11/4097
- IPC分类号: G11C11/4097
摘要:
A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.