发明授权
US4937826A Method and apparatus for sensing defects in integrated circuit elements
失效
用于感测集成电路元件缺陷的方法和装置
- 专利标题: Method and apparatus for sensing defects in integrated circuit elements
- 专利标题(中): 用于感测集成电路元件缺陷的方法和装置
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申请号: US242848申请日: 1988-09-09
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公开(公告)号: US4937826A公开(公告)日: 1990-06-26
- 发明人: Tushar R. Gheewala , Robert J. Lipp
- 申请人: Tushar R. Gheewala , Robert J. Lipp
- 申请人地址: CA San Jose
- 专利权人: CrossCheck Technology, Inc.
- 当前专利权人: CrossCheck Technology, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: G01R31/26
- IPC分类号: G01R31/26 ; G01R31/30 ; G01R31/316 ; G01R31/317 ; G01R31/3185 ; G06F11/22 ; H01L21/66
摘要:
An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults. A method according to the invention includes path sensitization whereby test patterns can be reduced to Boolean expressions.
公开/授权文献
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