发明授权
US4949239A System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system 失效
在多处理器计算机系统中实现同步挂起总线上的多个锁定指示器的系统

System for implementing multiple lock indicators on synchronous pended
bus in multiprocessor computer system
摘要:
A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
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