A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.