Externally inputted data of one word line is temporarily stored in a latch circuit. In the writing cycle, the data stored and held in the latch circuit is collectively written in memory transistors connected to the selected word line. On this occasion, 0 V is applied to one of the control gate and the drain of the memory transistor in which "0" is written and a high voltage V.sub.PP is applied to the other of the control gate and the drain. Therefore, not only in the erasing cycle but also in the writing cycle, the operation is carried out by the movement of charges caused by the electron tunneling.