发明授权
- 专利标题: Fabrication of CMOS devices with reduced gate length
- 专利标题(中): 减少栅极长度的CMOS器件的制造
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申请号: US381283申请日: 1989-07-18
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公开(公告)号: US4987088A公开(公告)日: 1991-01-22
- 发明人: Carlo Bergonzoni , Tiziana Cavioni , Giuseppe P. Crisenza
- 申请人: Carlo Bergonzoni , Tiziana Cavioni , Giuseppe P. Crisenza
- 申请人地址: ITX Agrate Brianza
- 专利权人: SGS-Thomson Microelectronics S.r.l.
- 当前专利权人: SGS-Thomson Microelectronics S.r.l.
- 当前专利权人地址: ITX Agrate Brianza
- 优先权: ITX83653A/88 19880729
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L21/8238 ; H01L27/105
摘要:
A process for fabricating CMOS integrated devices includes forming an n-type deep well diffusion region in a surface of a p-type monocrystalline silicon substrate. Transistor devices having a p-type channel region are formed within the deep well diffusion regions, and transistor devices having an n-type channel region are formed external the deep well diffusion regions. The improvement of the present invention includes the step of performing an unmasked ion implantation of boron over the entire surface of the monocrystalline silicon substrate after having formed the deep well diffusion regions in order to effect simultaneously a partial compensation of a superficial doping level of the deep well diffusion region and an enrichment of a superficial doping level of the monocrystalline silicon substrate external the deep well diffusion region.
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