公开(公告)号：US6150853A

公开(公告)日：2000-11-21

申请号：US394688

申请日：1995-02-27

Applicant: Francesco Chrappan ,  Maurizio Nessi ,  Alberto Salina

Inventor： Francesco Chrappan ,  Maurizio Nessi ,  Alberto Salina

IPC: H03F3/20 ,  H02P25/034 ,  H03F1/32 ,  H03F3/30 ,  H03F3/347 ,  H03K3/00

CPC classification number: H03F3/3062 ,  H02P25/034 ,  H03F1/3217 ,  H03F3/3037 ,  H03F2203/30057 ,  H03F2203/30096 ,  H03F2203/30129

Abstract: The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.

Abstract translation: 通过驱动外部连接的功率晶体管通过电平移位缓冲器来控制AB类放大器的外部连接的输出功率晶体管的操作，而不采用输出电流的任何外部感测电阻，并采用由由 信号放大级的输出和与其漏极串联的电阻。 缓冲级将外部功率晶体管的驱动信号的电平移动到等于限制网络的集成晶体管的阈值电压的值，从而确保在静态条件下外部功率晶体管的截止。

公开(公告)号：US6147380A

公开(公告)日：2000-11-14

申请号：US521867

申请日：2000-03-08

Applicant: Paolo Cappelletti

Inventor： Paolo Cappelletti

IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract translation: 包括至少一个浮栅晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层 。 栅极氧化物从衬底隔离浮栅区域。 浮栅区域耦合到控制栅极端子。 存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

公开(公告)号：US6111429A

公开(公告)日：2000-08-29

申请号：US79131

申请日：1998-05-14

Applicant: Luca Bertolini

Inventor： Luca Bertolini

IPC: H03K3/356 ,  H03K17/10 ,  H03K19/0175

CPC classification number: H03K3/356113 ,  H03K17/102

Abstract: A circuit for shifting the voltage level of a digital signal, comprising a first pair of transistors of a first polarity, which are connected to a high-voltage line, and a second pair of transistors of a second polarity, which are connected to a ground line; the first and second pairs of transistors are connected to each other by means of the drain terminals of the respective transistors; an input voltage is applied to the gate terminals of the first pair of transistors. The circuit further includes a secondary circuit for leveling the gate voltages of the transistors of the first and second pairs, which is connected between the first and second pairs of transistors and whereto at least one reference voltage is applied. The circuit also includes an output stage, whose output is a voltage which is shifted in level with respect to the input voltage. The secondary circuit limits the gate-source voltage value of the first pair of transistors to a value which is independent of the voltage value of the high-voltage line, so as to prevent damage to the first pair of transistors.

Abstract translation: 一种用于移动数字信号的电压电平的电路，包括连接到高电压线的第一极性的第一对晶体管和第二极性的第二对晶体管连接到地 线; 第一和第二对晶体管通过相应晶体管的漏极端子彼此连接; 输入电压被施加到第一对晶体管的栅极端子。 该电路还包括用于对连接在第一和第二对晶体管之间的第一和第二对晶体管的栅极电压进行调平的次级电路，并且至少施加至少一个参考电压。 电路还包括输出级，其输出是相对于输入电压在电平上移位的电压。 次级电路将第一对晶体管的栅极 - 源极电压值限制为与高压线的电压值无关的值，以防止损坏第一对晶体管。

公开(公告)号：US06108381A

公开(公告)日：2000-08-22

申请号：US17413

申请日：1998-02-02

Applicant: Danilo Pau ,  Roberta Bruni ,  Roberto Sannino

Inventor： Danilo Pau ,  Roberta Bruni ,  Roberto Sannino

IPC: H04N5/92 ,  G06F17/30 ,  G06T9/00 ,  G06T9/40 ,  H03M7/30 ,  H04N7/01 ,  H04N7/26 ,  H04N7/28 ,  H04N7/32 ,  H04N7/50 ,  H14N7/12

CPC classification number: G06T9/008 ,  G06T9/40 ,  H04N19/423 ,  H04N19/61 ,  H04N19/94

Abstract: A method for reducing the RAM requirement for temporarily storing a stream of data blocks in a coding/decoding system of information transferable by blocks, includes the steps of: compressing and coding the data by blocks through a tree search vector quantization (TSVQ); storing TSVQ compressed and coded data in the RAM; and decoding and decompressing in a subsequent reading of the data stored in the RAM the coded and compressed data, thereby reconstituting the stream of digital data blocks. The method may include fixing a certain scanning path of each data block of the stream to be decomposed into vectors of preestablished dimensions; coding the first vector of the scanning of a certain block of data in an unmodified manner; generating a replica vector of the last coded vector and calculating a prediction error vector; quantizing according to a binary search in a table of read-only quantized vectors the prediction error, by coding its address in the table; and repeating several of the steps for all the vectors of the scanning of each input data block.

Abstract translation: 一种减少用于将数据块流临时存储在块可传输信息的编码/解码系统中的RAM要求的方法，包括以下步骤：通过树搜索矢量量化（TSVQ）对数据进行压缩和编码; 将TSVQ压缩和编码数据存储在RAM中; 并且在随后读取存储在RAM中的数据的解码和解压缩编码和压缩数据，从而重构数字数据块流。 该方法可以包括将要分解的流的每个数据块的特定扫描路径固定成预先建立的维度的向量; 以未修改的方式对特定数据块的扫描的第一向量进行编码; 生成最后编码矢量的副本矢量并计算预测误差矢量; 根据在只读量化矢量的表中的二进制搜索量化量化该预测误差，通过对其表中的地址进行编码; 并且对于每个输入数据块的扫描的所有向量重复若干步骤。

公开(公告)号：US6081184A

公开(公告)日：2000-06-27

申请号：US28738

申请日：1998-02-24

Applicant: Rosario Scollo

Inventor： Rosario Scollo

IPC: B06B1/02 ,  B60Q5/00 ,  G08B3/10

CPC classification number: B06B1/0207 ,  B60Q5/00 ,  G08B3/10 ,  B06B2201/40 ,  B06B2201/53

Abstract: A self-protected, low emission electronic device for driving a warning horn includes a coil powered from a battery through a control push-button adapted for operation by a user and included in an electric connection between a terminal of the coil and the battery. The device includes a protective circuit portion connected between the battery and the warning horn. The protective circuit portion includes a bridge structure of power components. At least a pair of the power components are MOS power transistors of which one is driven by a charge pump.

Abstract translation: 用于驱动警告喇叭的自保护低发射电子设备包括由电池供电的线圈，其通过适于用户操作并包括在线圈的端子与电池之间的电连接中的控制按钮。 该装置包括连接在电池和警告喇叭之间的保护电路部分。 保护电路部分包括功率部件的桥结构。 至少一对功率部件是由功率泵驱动的MOS功率晶体管。

公开(公告)号：US6075402A

公开(公告)日：2000-06-13

申请号：US946727

申请日：1997-10-08

Applicant: Andrea Ghilardelli ,  Jacopo Mulatti ,  Stefano Ghezzi

Inventor： Andrea Ghilardelli ,  Jacopo Mulatti ,  Stefano Ghezzi

IPC: H02M3/07 ,  G05F1/10

CPC classification number: H02M3/073

Abstract: A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.

Abstract translation: 电荷泵包括串联连接的多个级，电荷泵的输入端连接到电压源，电荷泵的输出端提供高于电压源的输出电压。 每个级包括连接在级输入端和级输出端之间的单向电流MOS晶体管装置，允许电流仅从所述级输入端流向所述级输出端;以及第一电容器，其一板连接到所述级输出端，以及 由相应的第一数字信号驱动的另一个板，周期性地在接地和所述电压源之间切换。 级的单向电流MOS晶体管装置具有独立的体电极，并且提供偏置电压发生器电路，用于以相应的体积电位偏压所述单向电流流量MOS晶体管装置的体电极，其逐渐地从接近于 所述输入端子接近电荷泵的所述输出端子的级。

公开(公告)号：US6072665A

公开(公告)日：2000-06-06

申请号：US104744

申请日：1998-06-25

Applicant: Paolo Ferrari ,  Bruno Murari ,  Benedetto Vigna

Inventor： Paolo Ferrari ,  Bruno Murari ,  Benedetto Vigna

IPC: G11B21/21 ,  G11B5/55 ,  G11B21/10 ,  G11B21/12 ,  G11B21/24 ,  G11B5/48

CPC classification number: G11B21/12 ,  G11B21/24 ,  G11B5/5552 ,  G11B5/5582

Abstract: A suspension arm (125) for a head (120) of a disk storage device comprises at least one wall (225, 230) substantially perpendicular to the disk (105) and having a portion (238, 239) which is deformable parallel to a plane extending through a longitudinal axis (235) of the suspension arm (125) and perpendicular to the at least one wall (225, 230), and piezoelectric member (240, 255) which can deform the portion (238, 239) in order correspondingly to move the head (120), the piezoelectric member (240-255) being fixed to the portion (238, 239) of the at least one wall (225, 230).

Abstract translation: 用于磁盘存储装置的磁头（120）的悬架臂（125）包括至少一个基本上垂直于磁盘（105）的壁（225,230），并且具有可平行于磁盘的可变形的部分（238,239） 延伸穿过悬挂臂（125）的纵向轴线（235）并且垂直于至少一个壁（225,230）的平面以及可以按顺序使部分（238,239）变形的压电构件（240,255） 相应地移动头部（120），压电元件（240-255）固定在至少一个壁（225,230）的部分（238,239）上。

公开(公告)号：US6060940A

公开(公告)日：2000-05-09

申请号：US59973

申请日：1998-04-14

Applicant: Giorgio Chiozzi

Inventor： Giorgio Chiozzi

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/161 ,  H03K17/6872

Abstract: A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.

Abstract translation: CMOS输出级，提供稳定的静态电流。 输出级包括将静态电流与功率NMOS晶体管和参考电流源的NMOS参考晶体管的通道几何形状相关联的电路。 该配置消除了在CMOS输出级使用的功率PMOS晶体管上的静态电流的依赖性，其阈值电压在高电流和电压操作下可随时间漂移，并且不利地影响静态电流稳定性。

公开(公告)号：US6043764A

公开(公告)日：2000-03-28

申请号：US8370

申请日：1998-01-16

Applicant: Roberto Sannino ,  Filippo Brenna

Inventor： Roberto Sannino ,  Filippo Brenna

IPC: G11B7/00 ,  G11B7/005 ,  G11B20/14 ,  H03M5/14 ,  H03M5/00 ,  H03M7/00

CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1465

Abstract: System for decoding code words in the EFM-PLUS and/or EFM format in which an enumeration block makes it possible to associate in a one-to-one manner with each of the code words a numerical value from a practically continuous set of numerical values. The numerical value, possibly summed with an offset value, by an address generator, addresses a read-only memory in which are stored information codes, each of which is associated, as decoded information, with one of the code words.

Abstract translation: 用于解码EFM-PLUS和/或EFM格式的码字的系统，其中枚举块使得可以以一对一的方式将每个码字与来自实际连续的数值集合的数值相关联 。 通过地址生成器可能与偏移值相加的数值可以将存储的信息代码（其中的每一个都作为解码信息）与其中一个代码字相关联的只读存储器。

公开(公告)号：US6041321A

公开(公告)日：2000-03-21

申请号：US953956

申请日：1997-10-10

Applicant: Vito Fabbrizio ,  Alan Kramer

Inventor： Vito Fabbrizio ,  Alan Kramer

IPC: G06F17/10 ,  G06N3/063 ,  G06F15/18

CPC classification number: G06N3/063

Abstract: An electronic device for performing convolution operations comprises shift registers for receiving binary input values representative of an original matrix, synapses for storing weights correlated with a mask matrix, and neurons for outputting a binary result dependent on the sum of the binary values weighted by the synapses. Each synapse has a conductance correlated with the weight stored and dependent upon the binary input value. Each neuron generates the binary result in dependence on the total conductance of the corresponding synapses.

Abstract translation: 用于执行卷积运算的电子装置包括用于接收表示原始矩阵的二进制输入值的移位寄存器，用于存储与掩模矩阵相关的权重的突触，以及用于输出取决于由突触加权的二进制值之和的二进制结果的神经元 。 每个突触具有与存储的权重相关的电导，并且取决于二进制输入值。 每个神经元根据相应突触的总电导产生二进制结果。