发明授权
- 专利标题: Method of diagnosing integrated logic circuit
- 专利标题(中): 诊断集成逻辑电路的方法
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申请号: US84153申请日: 1987-08-12
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公开(公告)号: US4996659A公开(公告)日: 1991-02-26
- 发明人: Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
- 申请人: Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX61-192884 19860820; JPX61-219169 19860919
- 主分类号: G01R31/305
- IPC分类号: G01R31/305 ; G01R31/3193
摘要:
A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.
公开/授权文献
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