Invention Grant
US4998242A Virtual tributary cross connect switch and switch network utilizing the
same
失效
虚拟支路交叉连接交换机和交换机网络利用相同
- Patent Title: Virtual tributary cross connect switch and switch network utilizing the same
- Patent Title (中): 虚拟支路交叉连接交换机和交换机网络利用相同
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Application No.: US283178Application Date: 1988-12-09
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Publication No.: US4998242APublication Date: 1991-03-05
- Inventor: Daniel C. Upp
- Applicant: Daniel C. Upp
- Applicant Address: CT Shelton
- Assignee: TranSwitch Corp.
- Current Assignee: TranSwitch Corp.
- Current Assignee Address: CT Shelton
- Main IPC: H04Q3/52
- IPC: H04Q3/52 ; H04J3/06 ; H04J3/16 ; H04Q11/04
Abstract:
Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses. When the bus phase is indicative of the VT destination of the data, the data is sent to the output bus dictated by the space switch connection. Phase switching is obtained by determining the difference in phase of the incoming VT as defined by the tagged V5 byte and the phase of the synchronous clocked output bus. The phase difference permits a VT frame pointer to be correctly generated. To establish component and system operation and timing, a system bit clock and multiframe clock are provided, with the internal clock of each component in a network chain being advanced one bit clock relative to its adjacent lower component.
Public/Granted literature
- US5437502A Utility holder Public/Granted day:1995-08-01
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