公开(公告)号：US6134653A

公开(公告)日：2000-10-17

申请号：US64446

申请日：1998-04-22

Applicant: Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

Inventor： Subhash C. Roy ,  Paul Hembrook ,  Eugene L. Parrella ,  Richard Mariano

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/462

Abstract: A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles. In addition, one set of general purpose registers can be loaded by a coprocessor while another set of general purpose registers is in use by the ALU. According to a presently preferred embodiment, each of the three sets of general purpose registers includes twenty-eight thirty-two bit registers. In addition, according to the presently preferred embodiment, a single set of four thirty-two bit registers is provided for use in any context. The set of common registers is used to store information which is used by more than one context.

Abstract translation: RISC处理器包括定序器，寄存器ALU（RALU），数据RAM和协处理器接口。 定序器包括一个Nx32位指令RAM，它通过协处理器接口从外部存储器引导。 RALU包括用于存储三个上下文的四端口寄存器文件和一个ALU。 根据本发明的ISA（指令集架构）支持多达八个协处理器。 本发明的一个重要特征是提供多组通用寄存器用于存储若干上下文。 根据目前的优选实施例，提供三组通用寄存器作为RALU的一部分，并且提供新的操作码用于在通用寄存器组之间切换。 使用多组通用寄存器，可以在三个处理周期内完成上下文切换。 此外，一组通用寄存器可由协处理器加载，另一组通用寄存器由ALU使用。 根据目前优选的实施例，三组通用寄存器中的每一个包括二十八位32位寄存器。 另外，根据目前的优选实施例，提供了一组四个32位寄存器，用于任何上下文。 该公共寄存器集用于存储由多个上下文使用的信息。

公开(公告)号：US5893162A

公开(公告)日：1999-04-06

申请号：US796085

申请日：1997-02-05

Applicant: Joseph C. Lau ,  Subhash C. Roy ,  Dirk L. M. Callaerts ,  Ivo Edmond Nicole Vandeweerd

Inventor： Joseph C. Lau ,  Subhash C. Roy ,  Dirk L. M. Callaerts ,  Ivo Edmond Nicole Vandeweerd

IPC: G06F5/06 ,  G06F12/02 ,  H04L12/56 ,  H04Q11/04 ,  G06F12/00

CPC classification number: H04Q11/0478 ,  G06F12/023 ,  G06F5/065 ,  G06F2205/064 ,  H04L2012/5681

Abstract: Apparatus and methods for allocating shared memory utilizing linked lists are provided which are particularly useful in telecommunications applications such as ATM. A management RAM contained within a VLSI circuit is provided for controlling the flow of data into and out of a shared memory (data RAM), and stores information regarding a number of link lists and a free link list in the shared memory, and a block pointer to unused RAM locations. A head pointer, tail pointer, block counter and empty flag are stored for each data link list. The head and tail pointers each include a block pointer and a position counter. The block counter contains the number of blocks used in the particular queue. The empty flag indicates whether the queue is empty. The free link list includes a head pointer, a block counter, and an empty flag. Each memory page of the shared data RAM receiving the incoming data includes locations for storing data. The last location of the last page in a block of shared data RAM memory is preferably used to store a next-block pointer plus parity information. If there are no more blocks in the queue, that last location is set to all ones. An independent agent is utilized in the background to monitor the integrity of the link list structure. Using the methods and apparatus of the invention, four operations are defined for ATM cell management: cell write, cell read, queue clear, and link list monitoring.

Abstract translation: 提供了利用链表分配共享存储器的装置和方法，其在诸如ATM的电信应用中特别有用。 包含在VLSI电路内的管理RAM被提供用于控制进出共享存储器（数据RAM）的数据流，并将关于多个链接列表和空闲链接列表的信息存储在共享存储器中，以及块 指向未使用的RAM位置。 为每个数据链接列表存储头指针，尾指针，块计数器和空标志。 头和尾指针各包括一个块指针和一个位置计数器。 块计数器包含特定队列中使用的块数。 空标志表示队列是否为空。 免费链接列表包括头指针，块计数器和空标志。 接收输入数据的共享数据RAM的每个存储器页面包括用于存储数据的位置。 共享数据RAM存储器块中的最后一页的最后位置优选地用于存储下一个块指针加上奇偶校验信息。 如果队列中没有更多块，则将最后一个位置设置为全部。 在后台使用独立代理来监视链接列表结构的完整性。 使用本发明的方法和装置，为ATM信元管理定义了四个操作：信元写入，信元读取，清除清单和链路列表监视。

公开(公告)号：US5615237A

公开(公告)日：1997-03-25

申请号：US308083

申请日：1994-09-16

Applicant: Sin-Min Chang ,  Eugene L. Parrella

Inventor： Sin-Min Chang ,  Eugene L. Parrella

IPC: H04J3/06 ,  H04L7/00

CPC classification number: H04J3/0608

Abstract: A synchronizer for telecommunications signals includes a telecommunications interface for receiving bits of a telecommunications signal having a frame, an SRAM which stores bit-defined states for a plurality of bit locations in the frame, a state update lookup table for changing the states for a plurality of the frame bit locations of the SRAM based on a previous state and based on an incoming bit of the telecommunications signal, and frame location identification logic for determining the location of the overhead bit of the telecommunications signal frame based on the states of the plurality of bit locations. In a first embodiment, the SRAM is an x by y bit SRAM, where x equals the number of bits in the frame, and y is large enough so that the number of possible states .ltoreq.2.sup.Y. In a second embodiment, the bit locations are divided into a plurality of subgroups or stages, and the SRAM is at least an Int (x/s) by y bit SRAM, where s is an integer greater than one which represents the number of stages of the state machine, and Int (x/s) is the quotient x/s rounded up. In the second embodiment, after the state of a bit location in a first stage reaches a predetermined value, the bits of an associated frame location are used for state updates in a second stage.

Abstract translation: 用于电信信号的同步器包括用于接收具有帧的电信信号的比特的电信接口，存储该帧中的多个位位置的位定义状态的SRAM，用于改变多个状态的状态更新查找表 基于先前状态并基于电信信号的输入位的SRAM的帧位位置，以及帧位置识别逻辑，用于基于多个信号的状态来确定电信信号帧的开销比特的位置 位位置。 在第一实施例中，SRAM是x×y位SRAM，其中x等于帧中的位数，并且y足够大，使得可能状态的数目为2Y。 在第二实施例中，位位置被分成多个子组或级，并且SRAM至少是由y位SRAM的Int（x / s），其中s是大于表示级数的整数 的状态机，Int（x / s）是向上舍入的商x / s。 在第二实施例中，在第一级中的比特位置的状态达到预定值之后，相关联的帧位置的比特用于第二级中的状态更新。

公开(公告)号：US4998242A

公开(公告)日：1991-03-05

申请号：US283178

申请日：1988-12-09

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04Q3/52 ,  H04J3/06 ,  H04J3/16 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H04J3/0623 ,  H04J3/1611

Abstract: Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses. When the bus phase is indicative of the VT destination of the data, the data is sent to the output bus dictated by the space switch connection. Phase switching is obtained by determining the difference in phase of the incoming VT as defined by the tagged V5 byte and the phase of the synchronous clocked output bus. The phase difference permits a VT frame pointer to be correctly generated. To establish component and system operation and timing, a system bit clock and multiframe clock are provided, with the internal clock of each component in a network chain being advanced one bit clock relative to its adjacent lower component.

Abstract translation: 提供利用多个相同的切换组件的交换组件和交换网络，用于跨多个基本SONET格式化信号的虚拟支路交叉连接。 交换组件各自接收至少一个SONET格式的信号，并且在标记V5字节的同时将该信号分解成其虚拟支路（VT）有效载荷分量。 VT数据以相位，时间和空间进行缓冲和切换，以实现交错连接到产生输出总线的SONET信号上，这些输出总线是通过组件运行的同步计时总线。 空间开关本质上是一个非阻塞开关矩阵。 时间切换是与每个输入VT相关联的比较装置，其基于同步时钟输出总线的相位将缓冲器中的数据的VT目的地与虚拟支路时间指示进行比较。 当总线相位指示数据的VT目的地时，数据被发送到由空间交换机连接指定的输出总线。 通过确定由标记的V5字节和同步时钟输出总线的相位定义的输入VT的相位差来获得相位切换。 相位差允许正确生成VT帧指针。 为了建立组件和系统操作和定时，提供了系统位时钟和多帧时钟，网络链中每个组件的内部时钟相对于其相邻的下部组件提前一位。

公开(公告)号：US6104724A

公开(公告)日：2000-08-15

申请号：US961932

申请日：1997-10-29

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04J3/16

CPC classification number: H04L12/403

Abstract: An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users. The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

Abstract translation: 异步数据传输和源流量控制系统包括总线主机和耦合到双向数据总线的多个总线用户。 总线主机为每个总线用户提供两个时钟信号，一个系统时钟和一个帧时钟。 帧时钟指定帧的开始。 帧格式优选地包括十五或十六个系统时钟周期，其中第一个被指定为请求字段，其中最后一个包括授权字段。 一个或多个其它周期可被分配控制和/或路由信息，并且其余周期包括固定长度的数据字段。 在请求字段期间，任何数量的总线用户可以请求由总线主机接收的访问。 在授权字段期间，总线主机授权对所选总线用户访问下一帧的整个数据部分。 根据总线主机中可能对总线用户不了解的仲裁算法确定哪个用户被授权访问下一个帧。 异步数据传输和源流量控制系统在适应BISDN系统中使用的ATM信元的内容传输方面具有特殊的应用。

公开(公告)号：US5774465A

公开(公告)日：1998-06-30

申请号：US650910

申请日：1996-05-17

Applicant: Joseph C. Lau ,  Subhash C. Roy

Inventor： Joseph C. Lau ,  Subhash C. Roy

IPC: H04L12/56 ,  H04Q11/04

CPC classification number: H04L49/3009 ,  H04L49/201 ,  H04L49/203 ,  H04L49/3081 ,  H04L49/30

Abstract: An ATM destination switch includes an ATM layer device coupled to a physical layer device. The ATM layer device includes a ATM layer interface which receives incoming ATM cells, a processor which is typically with an associated translation RAM, and an ATM layer to physical layer interface. The processor decodes the incoming ATM cell to obtain a VPI/VCI, and provides additional routing information (session number) for the cell for multicast purposes. The cell with the additional routing information is forwarded to the physical layer device which has a header processor, a multicast indicator storage table, preferably in the form of a bit map, for storing output line indications by session number, and a plurality of ATM line output interfaces. The header processor receives the cell with the additional routing information, reads the additional routing information, accesses the multicast indicator storage table based on the additional routing information to determine to which output lines the cell is to be provided, and controls the copying of the cell for each output line so that it may be received at multiple destinations. Thus, an incoming cell which is to be multicast to multiple users connected to the physical layer side of the switch will be multicast to the multiple users using the single VPI/VCI chosen for the local multicast.

Abstract translation: ATM目的地交换机包括耦合到物理层设备的ATM层设备。 ATM层设备包括接收进入的ATM信元的ATM层接口，通常具有相关联的转换RAM的处理器，以及ATM层到物理层接口。 处理器对输入的ATM信元进行解码以获得VPI / VCI，为组播目的提供小区的附加路由信息（会话号）。 具有附加路由信息的小区被转发到物理层设备，该物理层设备具有头处理器，多播指示符存储表，优选地以位图的形式，用于通过会话号存储输出线指示，以及多个ATM线 输出接口。 标题处理器接收具有附加路由信息的小区，读取附加路由信息，基于附加路由信息访问多播指示符存储表，以确定要向其提供小区的哪条输出线，并控制小区的复制 对于每个输出线，使得其可以在多个目的地被接收。 因此，要使用连接到交换机的物理层侧的多个用户进行组播的传入单元将使用为本地组播选择的单个VPI / VCI向多个用户进行多播。

公开(公告)号：US5331641A

公开(公告)日：1994-07-19

申请号：US848384

申请日：1992-03-09

Applicant: Bidyut Parruck ,  Robert W. Hamlin, Jr.

Inventor： Bidyut Parruck ,  Robert W. Hamlin, Jr.

IPC: H04J3/07 ,  G06F5/10 ,  G06F5/12 ,  H04J3/00 ,  H04J3/06 ,  H04J3/16 ,  H04L25/05 ,  H04J14/08

CPC classification number: H04J3/076 ,  G06F5/12 ,  H04J3/0623 ,  H04J3/1611 ,  H04L25/05 ,  G06F2205/123

Abstract: Apparatus and methods for retiming an STS-3 type signal are provided. The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs, and a byte which is synchronous with the TOH is tracked through the three FIFOs to provide an indication of the FIFO depth. A frame count is also kept to track the number of frames since a last pointer movement. Stuffs or destuffs are generated based on the FIFO depth as well as based on the frame count, with a stuff or destuff generated as quickly as four frames from a previous pointer movement if the FIFO is close to full or close to empty, and less quickly (e.g., at thirty-two frames from a previous pointer movement) if the FIFO is only starting to empty or to fill. Where the STS-3 type signal is a STS-3C signal, the decision on whether to stuff or destuff is made with reference to all three depth measurement circuits as all the STS-1 payloads must be stuffed or destuffed together. Also, to realign the STS-1 components of the STS-3C signal, the J1 bytes of the signal are tracked through the FIFOs, and a logic circuit is provided having phase 3 of the outgoing STS-3 clock, and the three J1 byte control signals as inputs. The logic circuit inhibits a read of a J1 byte from any particular FIFO unless all FIFO's have a high J1 signal at phase 3 of the clock.

Abstract translation: 提供了重新定时检测STS-3型信号的装置和方法。 输入的STS-3型信号的SPE被解复用为三个STS-1有效载荷并馈送到三个FIFO，并且通过三个FIFO跟踪与TOH同步的字节，以提供FIFO深度的指示。 帧计数也保持跟踪自从最后一个指针移动以来的帧数。 基于FIFO深度以及基于帧计数产生的填充或解消息，如果FIFO接近满或接近空，则从前一个指针移动快速生成四帧的填充或消息，并且不太快 （例如，从先前的指针移动开始的三十二帧），如果FIFO只开始清空或填满。 在STS-3型信号为STS-3C信号的情况下，由于所有STS-1有效载荷必须填充或混合在一起，因此参照所有三个深度测量电路进行是否进行填充或消除的决定。 另外，为了重新调整STS-3C信号的STS-1分量，通过FIFO跟踪信号的J1字节，并且提供具有输出STS-3时钟的相位3的逻辑电路，以及三个J1字节 控制信号作为输入。 逻辑电路禁止从任何特定FIFO读取J1字节，除非所有FIFO在时钟的相位3具有高J1信号。

公开(公告)号：US5157655A

公开(公告)日：1992-10-20

申请号：US606482

申请日：1990-10-31

Applicant: Robert W. Hamlin, Jr. ,  Daniel C. Upp

Inventor： Robert W. Hamlin, Jr. ,  Daniel C. Upp

IPC: G06F5/10 ,  G06F5/14 ,  H04J3/07 ,  H04L25/05

CPC classification number: G06F5/14 ,  H04J3/076 ,  H04L25/05 ,  G06F2205/061

Abstract: An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO for receiving the data component of the STS-1 signal, a measuring circuit having an input clock related to the STS-1 signal and the output clock of the apparatus as inputs for effectively measuring the relative fullness of the FIFO, and a voltage controlled crystal oscillator (VCXO) for receiving a control signal from the measuring circuit and for generating the output clock of the apparatus in response thereto, where data in the FIFO is taken out of the FIFO as the DS-3 signal according to the rate of the output clock. The FIFO is preferably a byte wide RAM, and the measuring circuit is comprised of two counters, an XOR gate, and a low pass filter. One counter receives the apparatus output clock as its input, while the other counter receives a gapped STS-1 data payload input clock as its input. The msb's of the counters are compared by the XOR gate, and the duty cycle of the XOR gate output provides an indication of the difference between the rates of the input and output clocks. The low pass filter filters out high frequency changes in the duty cycle due to the gaps in the input clock, and provides the VCXO with a dc signal which changes with the long term average of the duty cycle. In response to this dc signal, the VCXO changes the output clock rate. By feeding back the output clock to one of the counters of the measuring circuit, a closed loop system is established.

Abstract translation: 提供了一种接收STS-1信号的间隙数据分量并从其提供无间隙DS-3数据信号的装置，并且包括用于接收STS-1信号的数据分量的FIFO，具有输入时钟相关的测量电路 将STS-1信号和装置的输出时钟作为输入，用于有效测量FIFO的相对丰满度;以及压控晶体振荡器（VCXO），用于从测量电路接收控制信号并产生输出时钟 响应于此的装置，其中根据输出时钟的速率将FIFO中的数据作为DS-3信号从FIFO中取出。 FIFO优选地是一个宽字节的RAM，并且测量电路由两个计数器，XOR门和低通滤波器组成。 一个计数器接收设备输出时钟作为其输入，而另一个计数器接收有间隙STS-1数据有效载荷输入时钟作为其输入。 计数器的msb被异或门比较，异或门输出的占空比提供了输入和输出时钟速率差异的指示。 低通滤波器滤除了由于输入时钟间隙引起的占空比的高频变化，并为VCXO提供了一个随着占空比长期平均值而变化的直流信号。 响应于该直流信号，VCXO改变输出时钟速率。 通过将输出时钟反馈到测量电路的一个计数器，建立闭环系统。

公开(公告)号：US4914429A

公开(公告)日：1990-04-03

申请号：US283173

申请日：1988-12-09

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04Q3/52 ,  H03K17/693 ,  H04J3/06 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H03K17/693 ,  H04J3/0685

Abstract: A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size. The use of multiple stages is permitted as the clock regeneration means associated with each port prevents signal dispersion and signal clock skew. The passing and switching of clock signals along with the data also permits the switching matrix to simultaneosuly handle lines having different rates, provided that a line of a given rate which is an input to the switching network must be connected to another line of the same rate which is an output of the switching network.

Abstract translation: 提供了一种优选集成电路形式的开关元件。 开关组件具有多个入口和出口数据端口，其具有相关联的入口和出口时钟端口，用于每个出口数据端口的时钟再生器和触发器，以及用于耦合每个入口数据端口及其相关联的入口时钟端口的开关矩阵 到任何出口数据端口及其相关的插座时钟端口。 时钟再生装置获得离开切换核心的时钟信号并再生时钟信号波形。 根据再生的时钟信号，触发器使得离开开关核心的数据与其相关联的再生时钟信号同步地从开关部件中输出。 多个相同的切换部件可以布置成具有多个级的折叠的Clos布置，以提供任何尺寸的期望的开关网络。 允许使用多级，因为与每个端口相关联的时钟再生装置防止信号色散和信号时钟偏移。 时钟信号与数据的通过和切换也允许交换矩阵同时处理具有不同速率的线路，只要作为交换网络的输入的给定速率的线路必须连接到相同速率的另一条线路 这是交换网络的输出。