发明授权
US5003286A Binary magnitude comparator with asynchronous compare operation and
method therefor
失效
具有异步比较运算的二进制幅度比较器及其方法
- 专利标题: Binary magnitude comparator with asynchronous compare operation and method therefor
- 专利标题(中): 具有异步比较运算的二进制幅度比较器及其方法
-
申请号: US390556申请日: 1989-08-07
-
公开(公告)号: US5003286A公开(公告)日: 1991-03-26
- 发明人: Joseph Carbonaro , R. A. Garibay, Jr. , Richard Reis , Jesse R. Wilson
- 申请人: Joseph Carbonaro , R. A. Garibay, Jr. , Richard Reis , Jesse R. Wilson
- 申请人地址: IL Schaumburg
- 专利权人: Motorola, Inc.
- 当前专利权人: Motorola, Inc.
- 当前专利权人地址: IL Schaumburg
- 主分类号: G06F7/02
- IPC分类号: G06F7/02 ; G11C15/00 ; G11C15/04
摘要:
A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.