公开(公告)号：US5003286A

公开(公告)日：1991-03-26

申请号：US390556

申请日：1989-08-07

申请人： Joseph Carbonaro ,  R. A. Garibay, Jr. ,  Richard Reis ,  Jesse R. Wilson

发明人： Joseph Carbonaro ,  R. A. Garibay, Jr. ,  Richard Reis ,  Jesse R. Wilson

IPC分类号： G06F7/02 ,  G11C15/00 ,  G11C15/04

CPC分类号： G06F7/026

摘要： A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.

摘要翻译： 具有多行和多列的二进制幅度比较器，包括最高有效列和最低有效列。 二进制幅度比较器不是与相应位大小的时钟二进制幅度比较器在较短的时间周期内进行异步运算并进行比较。 二进制幅度比较器包括形成多个行和列的多个比较器单元。 每一行对应一个寄存器，每一列在该寄存器中有一个位置。 通过选择具有耦合到最高有效列中的比较器单元的多个选择信号的一个或多个寄存器开始比较，并且从最高有效列继续到下一个最重要的列，并且当最不重要的比较时终止 列完成。 二进制幅度比较的结果是表示最高值寄存器的二进制值的第一输出信号和指示哪个行或哪一行具有最高值的第二输出信号。 二进制幅度比较器被设计为以任意数量的行和列进行操作。

公开(公告)号：US4972102A

公开(公告)日：1990-11-20

申请号：US348927

申请日：1989-05-08

申请人： Richard Reis ,  R. A. Garibay, Jr. ,  Jesse R. Wilson

发明人： Richard Reis ,  R. A. Garibay, Jr. ,  Jesse R. Wilson

IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/0185

CPC分类号： H03K19/01855 ,  H03K19/0016 ,  H03K19/01721

摘要： An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor. A discharging n-channel transistor is connected in series between the parallel network and ground. The gate of the discharging transistor is coupled to the sense node. The sense amplifier can enter a power-saving disable mode, and entry is controlled by a sense amplifier enable signal. This mode has two possible states corresponding to the state of the sense amplifier immediately preceding disablement and enables the sense amplifier to avoid output glitches when leaving the disabled mode. The sense amplifier uses two negative feedback loops, including the charging and discharging n-channel transistors, to limit the swing on the sense node, and this swing is substantially independent of the number of parallel transistors that are conductive.

摘要翻译： 公开了具有逻辑网络的集成电路，其具有耦合到感测节点并具有虚拟接地节点的输出，并且具有感测放大器，其具有耦合到感测节点的感测电路以提供输出信号，将耦合的反馈电路进行充电和放电 到限制读出放大器的摆幅的感测节点，以及启用和禁用感测放大器的使能控制。 在CMOS集成电路的一个实施例中，n沟道晶体管的并联网络具有连接到读出放大器的感测节点的输出。 感测反相器和反馈反相器连接到该感测节点。 反馈逆变器的开关点大大高于感测逆变器的开关点。 充电n沟道晶体管连接在感测节点和用于对感测节点充电的电源之间，反馈反相器的输出端连接到充电晶体管的栅极。 放电n沟道晶体管串联在并联网络和地之间。 放电晶体管的栅极耦合到感测节点。 读出放大器可进入省电禁止模式，输入由读出放大器使能信号控制。 该模式具有对应于紧接在禁止之前的读出放大器的状态的两个可能状态，并且使得读出放大器能够在离开禁用模式时避免输出毛刺。 读出放大器使用两个负反馈回路，包括充电和放电n沟道晶体管，以限制感测节点上的摆幅，并且该摆幅基本上与导电的并联晶体管的数量无关。

公开(公告)号：US20060005349A1

公开(公告)日：2006-01-12

申请号：US10888287

申请日：2004-07-09

申请人： Douglas Blocker ,  Keith Green ,  Richard Reis

发明人： Douglas Blocker ,  Keith Green ,  Richard Reis

IPC分类号： A47L5/34

CPC分类号： A47L5/34

摘要： A vacuum cleaner height adjustment mechanism including a cleaning head having a pair of laterally spaced front wheels and a pair of laterally spaced rear wheels mounted for rotation within the cleaning head for supporting the cleaning head on a floor during vacuum cleaning operations, the front wheels being mounted to a common axle mounted in the cleaning head for pivotal movement around a fixed axis, the wheels being mounted to the axle offset from the pivotal axis of the axle, an arm extending from the axle, a shaft mounted substantially horizontally in the cleaning head for rotation about a central axis disposed in a plane perpendicular to a plane containing the axis of the axle, one end of the shaft having spiral threads thereon and an opposite end having an adjustment knob fixed thereto for manually rotating the shaft, and a guide member having internal threads matching and engaged with the spiral threads on the shaft for movement along the shaft, the guide member being coupled to the arm extending from the axle so as to pivot the axle when the shaft is rotated by rotating the knob, whereby the front wheels are raised or lowered relative to the cleaning head.

摘要翻译： 一种真空吸尘器高度调节机构，包括具有一对横向间隔开的前轮的清洁头和一对安装成在清洁头内旋转的横向间隔开的后轮，用于在真空清洁操作期间将清洁头支撑在地板上，前轮是 安装在安装在清洁头中的公共轴上用于围绕固定轴线枢转运动，所述车轮安装到从轴的枢转轴线偏移的轴上，从车轴延伸的臂，大致水平地安装在清洁头中的轴 为了围绕设置在垂直于包含轴的轴线的平面的平面中的中心轴旋转，所述轴的一端具有螺旋线，并且具有固定到其上的用于手动旋转轴的调节旋钮的相对端，以及引导构件 其具有与所述轴上的所述螺旋螺纹相配合并与所述轴一起运动的内螺纹，所述引导构件联接到所述螺纹 所述臂从所述轴延伸，以便当所述轴通过旋转所述旋钮而旋转时枢轴，由此所述前轮相对于所述清洁头升高或降低。