A set of test vectors for input to a circuit (10) to test the integrity of each of its n interconnections (nets) 16 is generated by first ordering the nets. Thereafter, the vectors are generated by assigning the bits of each vector associated with a given net a one or zero such that the vector has a minimum weight, as compared to the vectors assigned to successive nets. Alternatively, the test vectors can be generated by assigning the bits of selected groups of vectors a one or zero such that the groups of vectors each have minimum potential weight and the vectors in the group are independent of each other. The successive groups of vectors are then concatenated to yield the test vector set.