公开(公告)号：US5331274A

公开(公告)日：1994-07-19

申请号：US80480

申请日：1993-06-24

Applicant: Najmi T. Jarwala ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Chi W. Yau

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/02

CPC classification number: G01R31/318513 ,  G01R31/318572

Abstract: Both the input/output connections (16) of a circuit board (10) and the boundary scan devices (12.sub.1 -12.sub.n) thereon can be tested simultaneously by boundary scan techniques using a Serial Test Extension Module (STEM) (28) which mates with the circuit board. The STEM (28) contains at least one boundary scan register (36) which makes an electrical connection with a separate circuit board input/output connection (16) when the STEM mates with the board. The boundary scan registers (36) within the STEM (28) are serially connected in a chain, that is, connected in series with a chain of serially connected boundary scan registers (20) within the boundary scan devices (12.sub.1 -12.sub.n). By launching a known bit stream into the chain of boundary scan registers (20) and (36) and thereafter shifting out the bits and comparing them to a reference bit stream, representing a defect-free condition, faults in the input/output connections (16) and/or in the devices (12.sub.1 -12.sub.n) can be detected.

Abstract translation: 电路板（10）的输入/输出连接（16）和其上的边界扫描装置（121-12n）都可以通过边界扫描技术同时测试，使用串行测试扩展模块（STEM）（28） 电路板。 STEM（28）包含至少一个边界扫描寄存器（36），当STEM与板匹配时，该边界扫描寄存器与单独的电路板输入/输出连接（16）进行电连接。 STEM（28）内的边界扫描寄存器（36）串联连接在链中，即与边界扫描设备（121-12n）内的串联连接的边界扫描寄存器（20）串联。 通过将已知比特流启动到边界扫描寄存器（20）和（36）链中，然后移出比特并将其与表示无缺陷条件的参考比特流进行比较，输入/输出连接中的故障 16）和/或在装置（121-12n）中。

公开(公告)号：US5444716A

公开(公告)日：1995-08-22

申请号：US113460

申请日：1993-08-30

Applicant: Najmi T. Jarwala ,  Paul A. Stiling ,  Enn Tammaru ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Paul A. Stiling ,  Enn Tammaru ,  Chi W. Yau

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/273 ,  H01L21/66

CPC classification number: G01R31/318566 ,  G06F11/273

Abstract: A system (10) for testing one or more circuit boards (12.sub.1 -12.sub.n), each containing at least one chain of Boundary-Scan cells (14.sub.1 -14.sub.p), includes a system test and diagnosis host (16) for managing overall testing of the system formed by the circuit boards. A Boundary-Scan Virtual Machine (BVM) (17) is operative to receive an initiate test command from the system test and diagnosis host independent of the number and nature of the boards to be tested. In response to the test command, the BVM (17) causes each circuit board to execute a test program (23) specific thereto to determine the errors, if any, in the board. The errors from each board are passed back to the BVM (17) which, in turn, interprets the errors to yield test information, indicative of the operation of the boards, which is then passed back to the system test and diagnosis host (16).

Abstract translation: 一种用于测试一个或多个电路板（121-12n）的系统（10），每个电路板包含至少一个边界扫描单元链（141-14p），包括用于管理整个测试的系统测试和诊断主机（16） 系统由电路板组成。 边界扫描虚拟机（BVM）（17）可操作以从系统测试和诊断主机接收启动测试命令，独立于要测试的板的数量和性质。 响应于测试命令，BVM（17）使每个电路板执行特定于其的测试程序（23）以确定板中的错误（如果有的话）。 每个板的错误被传回BVM（17），BVM（17）反过来解释错误以产生指示板的操作的测试信息，然后传递给系统测试和诊断主机（16） 。

公开(公告)号：US5029166A

公开(公告)日：1991-07-02

申请号：US359679

申请日：1989-05-31

Applicant: Najmi T. Jarwala ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Chi W. Yau

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66

CPC classification number: G01R31/31813 ,  G01R31/318558

Abstract: A test system (10) is associated with a chain of circuits (12) on a circuit board (13) for testing the interconnections (11) linking the circuits in the chain as well as for testing the interconnections linking them to those on other boards. The test system includes a controller (22) for generating a test signal and for capturing a response signal generated by the associated chain of circuits in response to the test signal. The controller (22) also generates a flow control signal which controls a network (24) that routes the test signals from the controller, or from a first other test system, to the associated chain of circuits (12). In accordance with the flow control signal, the network (24) also serves to route the response signal from the associated chain of circuits (12) to the controller (22) or to a second other test system. By selectively routing the test and response signals, the network (24) in each test system (10) allows individual testing of each associated chain of circuits or, alternatively, permits the chains of circuits on several boards to be effectively interconnected for testing.

公开(公告)号：US5155732A

公开(公告)日：1992-10-13

申请号：US594516

申请日：1990-10-09

Applicant: Najmi T. Jarwala ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Chi W. Yau

IPC: G06F11/22 ,  G01R31/3185

CPC classification number: G01R31/318555 ,  G01R31/318547 ,  G01R31/318572

Abstract: A scheme is provided for efficient transfer of N separate L-bit segments of data (where N and L are integers) to or from an L-bit register (14) in a device under test (10) serially coupled with at least one other register in a device (10') in a scan chain. To carry out such data transfer, a stream of N L-bit segments of interest is first concatenated to, and ahead of, a packet of L.sub.1 filler bits, where L.sub.1 is the cumulative number of register cells in the chain of devices (10') upstream of the L-bit register (14) in the device under test (10). The stream of L.sub.1 +NL bits is applied to the chain by shifting the first L.sub.1 bits of the block of NL bits through the chain to flush the previous data stored in the registers upstream of the L-bit register in the device under test (10). The remaining bits in the stream of L.sub.1 +NL bits are then shifted through the chain of devices (10 and 10' ) until the L.sub.1 filler bits have been shifted into the data registers of the devices (10') upstream of the device under test. An alternate data transfer scheme is also provided.

公开(公告)号：US5048021A

公开(公告)日：1991-09-10

申请号：US399132

申请日：1989-08-28

Applicant: Najmi T. Jarwala ,  Paul W. Rutkowski ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Paul W. Rutkowski ,  Chi W. Yau

IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  H05K13/08

CPC classification number: G01R31/318561 ,  G01R31/318555

Abstract: A method is disclosed for generating a control signal (TMS) which may be used to control the test activity of boundary scan system (10). The method is initiated by loading a multi-bit control macro (STI, DTI or DSTI) into a register (38) whose output is coupled back to its input. After loading of the macro, its identity is ascertained by a macro controller (42) which serves to decode a multi-bit signal (IT) whose state is indicative of the macro type. The macro controller (42) actuates the register to shift out the bits of the control macro in a sequence dependent on the macro's identity in order to generate the appropriate control signal. As each bit is shifted out, it is shifted back into the register so as to allow the same sequence of bits to be repeatedly shifted out.

公开(公告)号：US5027353A

公开(公告)日：1991-06-25

申请号：US339337

申请日：1989-04-17

Applicant: Najmi T. Jarwala ,  Chi W. Yau

Inventor： Najmi T. Jarwala ,  Chi W. Yau

IPC: G01R31/3183

CPC classification number: G01R31/318371

Abstract: A set of test vectors for input to a circuit (10) to test the integrity of each of its n interconnections (nets) 16 is generated by first ordering the nets. Thereafter, the vectors are generated by assigning the bits of each vector associated with a given net a one or zero such that the vector has a minimum weight, as compared to the vectors assigned to successive nets. Alternatively, the test vectors can be generated by assigning the bits of selected groups of vectors a one or zero such that the groups of vectors each have minimum potential weight and the vectors in the group are independent of each other. The successive groups of vectors are then concatenated to yield the test vector set.

Abstract translation: 通过首先对网络进行排序来生成用于输入到电路（10）以测试其n个互连（网络）16中的每一个的完整性的一组测试向量。 此后，与分配给连续网络的向量相比，通过将与给定网络相关联的每个向量的比特分配给一个或者零来生成向量，使得该向量具有最小权重。 或者，可以通过将所选择的一组向量的比特分配一个或者零来生成测试向量，使得每个向量组具有最小的电位权重，并且该组中的向量彼此独立。 然后将连续的载体组连接以产生测试载体集。

公开(公告)号：US4833677A

公开(公告)日：1989-05-23

申请号：US60882

申请日：1987-06-12

Applicant: Najmi T. Jarwala ,  Dhiraj K. Pradhan

Inventor： Najmi T. Jarwala ,  Dhiraj K. Pradhan

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/28

CPC classification number: G11C29/808 ,  G11C29/02 ,  G11C29/28 ,  G11C29/88 ,  G11C29/006

Abstract: The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The address, data and control signals are applied to the root node. The most significant address bit is decoded, generating either a left subtree or a right subtree select. The other signals would be buffered and propogated down the tree. The solution process occurs at each level within the bus until finally a single leaf node would be selected. Within the node, then, the internal timing and control unit would access the data requested, sending it up the tree or writing the value on the data bus, into the addressed location.

Abstract translation: RAM被划分为模块，每个模块显示为二进制互连网络的叶节点。 该网络携带地址/数据/控制总线，其允许节点在它们之间和外部世界之间进行通信。 地址，数据和控制信号应用于根节点。 最重要的地址位被解码，生成左子树或右子树选择。 其他信号将被缓冲并在树上传播。 解决过程发生在总线内的每个级别，直到最终将选择单个叶节点。 在节点内，则内部定时和控制单元将访问请求的数据，将其发送到树上或将数据写入数据总线上，到达寻址位置。