发明授权
- 专利标题： Output buffer circuits for reducing noise
- 专利标题（中）： 用于降低噪声的输出缓冲电路
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申请号： US427337申请日： 1989-10-27
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公开(公告)号： US5051625A公开(公告)日： 1991-09-24
- 发明人: Hiroshi Ikeda , Takashi Kimura , Norio Fujiki
- 申请人： Hiroshi Ikeda , Takashi Kimura , Norio Fujiki
- 申请人地址： JPX Yokohama
- 专利权人： Nissan Motor Co., Ltd.
- 当前专利权人： Nissan Motor Co., Ltd.
- 当前专利权人地址： JPX Yokohama
- 优先权： JPX63-272462 19881028; JPX1-53315 19890306; JPX1-88636 19890407
- 主分类号： H03K19/003
- IPC分类号： H03K19/003
摘要：
An output buffer circuit, in which a pair of current sources is connected to positive and negative power sources, and a first inverter having input and output terminals, is arranged between the current sources, in which a second inverter having input and output terminals, is connected to the output terminal of the first inverter, the second inverter including at least one of P-channel and N-channel MOSFETs, and a capacitor is connected between the input and output terminals of the second inverter.
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