发明授权
- 专利标题: Method for fabricating silicon-on-insulator structures
- 专利标题(中): 绝缘体上硅结构的制造方法
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申请号: US678390申请日: 1991-04-01
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公开(公告)号: US5057450A公开(公告)日: 1991-10-15
- 发明人: Gary B. Bronner , Paul M. Fahey , Bernard S. Meyerson , Wilbur D. Pricer
- 申请人: Gary B. Bronner , Paul M. Fahey , Bernard S. Meyerson , Wilbur D. Pricer
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: H01L21/762
- IPC分类号: H01L21/762 ; H01L21/306 ; H01L21/308 ; H01L21/763 ; H01L21/764 ; H01L27/12
摘要:
A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers. An oxidation step is then performed to form a bottom insulator consisting of the oxidized first p++ silicon layer and on an upper insulator consisting of the oxidized second p++ silicon layer.
公开/授权文献
- US5851925A Staining technique for semiconductor device for sem exposure 公开/授权日:1998-12-22
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