发明授权
US5075242A Method of manufacturing CMOS semiconductor device having decreased
diffusion layer capacitance
失效
具有降低的扩散层电容的CMOS半导体器件的制造方法
- 专利标题： Method of manufacturing CMOS semiconductor device having decreased diffusion layer capacitance
- 专利标题（中）： 具有降低的扩散层电容的CMOS半导体器件的制造方法
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申请号： US450570申请日： 1989-12-14
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公开(公告)号： US5075242A公开(公告)日： 1991-12-24
- 发明人: Moriya Nakahara
- 申请人： Moriya Nakahara
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX63-318637 19881219
- 主分类号： H01L21/265
- IPC分类号： H01L21/265 ; H01L21/8238 ; H01L27/092
摘要：
A method of manufacturing a CMOS semiconductor device includes the step of preparing a substrate having a first region of a second conductivity type serving as prospective source and drain formation regions of a transistor of a first conductivity type, and a second region of the first conductivity type serving as a prospective channel formation region of a transistor of the second conductivity type. The method of manufacturing the device further includes the steps of simultaneously doping an impurity of the first conductivity type having a first concentration in a first depth of each of the first and second regions, and doping an impurity of the first conductivity type having a concentration higher than the first concentration in a second depth smaller than the first depth of the first region.
公开/授权文献
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