公开(公告)号：US4916504A

公开(公告)日：1990-04-10

申请号：US907163

申请日：1986-09-15

申请人： Moriya Nakahara

发明人： Moriya Nakahara

IPC分类号： H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0688

摘要： A semiconductor device comprises a semiconductor substrate of first conductivity type with a major surface having an element isolation region formed on it. It further comprises island regions formed in the major surface region of said substrate and electrically isolated by said element isolation region, source and drain regions of second conductivity type formed in at least one of said island regions and electrically isolated from each other, thereby defining a channel region between them, a first gate insulating film formed on that surface portion of said island region in which at least said channel region is formed, a first gate electrode formed on said gate insulating film, a second gate insulating film formed on said gate electrode, an active layer made of recrystallized polysilicon, formed on said second gate insulating film, and consisting of source and drain regions of the first conductivity type and a channel region of the second conductivity type sandwiched between the source and drain regions, a third gate insulating film formed on that surface portion of said active layer in which at least the channel region is formed, and a second gate electrode formed on said third gate insulating film and connected to said first gate electrode.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，其主表面上形成有元件隔离区。 它还包括形成在所述衬底的主表面区域中并由所述元件隔离区电源隔离的岛区，其形成在所述岛区域中的至少一个中并且彼此电隔离的第二导电类型源区和漏区， 沟道区域，形成在形成有至少所述沟道区的所述岛区域的表面部分上的第一栅极绝缘膜，形成在所述栅极绝缘膜上的第一栅电极，形成在所述栅极上的第二栅极绝缘膜 形成在所述第二栅极绝缘膜上并且由所述第一导电类型的源极和漏极区域以及夹在所述源极和漏极区域之间的所述第二导电类型的沟道区域构成的由再结晶多晶硅制成的有源层，第三栅极绝缘 形成在至少形成有沟道区域的所述有源层的表面部分上的膜 形成在所述第三栅极绝缘膜上并连接到所述第一栅电极的栅极电极。

公开(公告)号：US4663827A

公开(公告)日：1987-05-12

申请号：US810785

申请日：1985-12-19

申请人： Moriya Nakahara

发明人： Moriya Nakahara

IPC分类号： H01L29/78 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L29/66477 ,  H01L21/32105 ,  H01L21/76888

摘要： A polycrystalline silicon layer is formed on a surface of a gate oxide film on a silicon substrate. A mask is formed on a prospective gate region of the polycrystalline silicon layer. Nitrogen is ion-implanted using the mask into a portion of the polycrystalline silicon layer excluding the prospective gate region. In addition, an impurity for forming source and drain regions is ion-implanted into portions of the substrate. The ion-implanted nitrogen is then annealed to convert the portion of the substrate in which nitrogen has been ion-implanted into an electrically insulating layer. The portion in which no nitrogen has been ion-implanted functions as a gate electrode. An upper portion of the polycrystalline silicon layer is etched using the mask before the nitrogen is annealed. Thus, the upper surfaces of the insulating layer and the gate electrode can be level with each other after annealing.

摘要翻译： 在硅衬底上的栅极氧化膜的表面上形成多晶硅层。 在多晶硅层的预期栅极区域上形成掩模。 使用掩模将氮离子注入除了预期栅极区域之外的多晶硅层的一部分。 此外，用于形成源区和漏区的杂质被离子注入到衬底的部分中。 然后将离子注入的氮退火以将其中已经将氮离子注入的衬底的部分转化成电绝缘层。 没有氮离子注入的部分用作栅电极。 在氮退火之前，使用掩模蚀刻多晶硅层的上部。 因此，绝缘层和栅电极的上表面在退火之后可以相互水平。

公开(公告)号：US5110762A

公开(公告)日：1992-05-05

申请号：US376655

申请日：1989-07-07

申请人： Moriya Nakahara ,  Yasuyuki Saito ,  Kenichi Shirai ,  Yasushi Itabashi ,  Takashi Turugai

发明人： Moriya Nakahara ,  Yasuyuki Saito ,  Kenichi Shirai ,  Yasushi Itabashi ,  Takashi Turugai

IPC分类号： H01L21/768

CPC分类号： H01L21/76819 ,  H01L21/76877

摘要： A method of manufacturing wiring layers of semiconductor devices in which a base layer made of electroconductive material is formed on a wiring-intended area of the substrate surface and an insulating layer is formed on the area other than the wiring intended area. Then the wiring layer is grown on the base layer up to substantially the same level as that of the insulating layer up, hereby planarity of the surfaces of the device is maintained after wiring formation.

摘要翻译： 一种制造半导体器件的布线层的方法，其中在基片表面的布线预定区域上形成由导电材料制成的基底层，并且在布线预期区域以外的区域上形成绝缘层。 然后将布线层在基层上生长达到与绝缘层向上基本相同的水平，因此在布线形成之后维持器件表面的平面性。

公开(公告)号：US4697333A

公开(公告)日：1987-10-06

申请号：US830831

申请日：1986-02-19

申请人： Moriya Nakahara

发明人： Moriya Nakahara

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/308

CPC分类号： H01L29/6659 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/32155 ,  H01L29/1083 ,  H01L29/78 ,  Y10S148/061 ,  Y10S148/082

摘要： A method of manufacturing a semiconductor device has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a portion of predetermined thickness of the polycrystalline silicon layer into an amorphous silicon layer, patterning the polycrystalline silicon layer, either all of which or a portion of predetermined thickness of which has been converted into an amorphous silicon layer, and ion-implanting an impurity in the semiconductor substrate using the patterned layer as a mask.

摘要翻译： 半导体器件的制造方法具有以下步骤：在半导体衬底上形成绝缘膜，在绝缘膜上形成多晶硅层，将多晶硅层的全部或多晶硅层的预定厚度的一部分转换为 非晶硅层，图案化多晶硅层，其全部或部分预定厚度已经转化为非晶硅层，并且使用图案化层作为掩模将半导体衬底中的杂质离子注入。

公开(公告)号：US5075242A

公开(公告)日：1991-12-24

申请号：US450570

申请日：1989-12-14

申请人： Moriya Nakahara

发明人： Moriya Nakahara

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  Y10T307/505

摘要： A method of manufacturing a CMOS semiconductor device includes the step of preparing a substrate having a first region of a second conductivity type serving as prospective source and drain formation regions of a transistor of a first conductivity type, and a second region of the first conductivity type serving as a prospective channel formation region of a transistor of the second conductivity type. The method of manufacturing the device further includes the steps of simultaneously doping an impurity of the first conductivity type having a first concentration in a first depth of each of the first and second regions, and doping an impurity of the first conductivity type having a concentration higher than the first concentration in a second depth smaller than the first depth of the first region.

摘要翻译： 一种制造CMOS半导体器件的方法包括以下步骤：制备具有第二导电类型的第一区域的衬底，其用作第一导电类型的晶体管的预期源极和漏极形成区域以及第一导电类型的第二区域 用作第二导电类型的晶体管的预期通道形成区域。 制造该器件的方法还包括以下步骤：在第一和第二区域的每一个的第一深度中同时掺杂具有第一浓度的第一导电类型的杂质，以及掺杂浓度更高的第一导电类型的杂质 比第一深度小于第一区域的第一深度的第二深度。