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发明授权
US5086018A Method of making a planarized thin film covered wire bonded semiconductor package 失效
制造平面化薄膜包覆导线键合半导体封装的方法

Method of making a planarized thin film covered wire bonded semiconductor package
摘要：
A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.
摘要（中）：

一种制造半导体芯片的方法，其中可以容易且可再现地改善芯片和引线框架之间的导线通过导线。 这是通过改善导线与引线框架构件之间的接合而实现的，并且通过在每个导线与其相应引线之间产生附加的接触，即使接合的接触在接合点处或紧邻接合点处断裂或失效。 这通过在每个芯片的有源表面上放置绝缘层来实现，该绝缘层在其上承载有引线框架导体已经通过接合线连接的输入和输出接合焊盘。 绝缘层是热固性粘合剂，并且放置在引线框架，接合线和半导体芯片的有源面之上，使得当层压力施加到绝缘层时，电线将被压碎并保持抵靠它们各自的焊盘，并且 抵靠它们连接的各个引线，并且被粘合剂保护的半导体的有源面与其结合。 以这种方式，电线和引线之间的更大的接触增强，并且导电性的缺陷或故障减少或消除。

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