An memory cell array includes a plurality of electrically erasable and programmable memory cell transistors which are arranged in a matrix form and each of which includes a source region, drain region, floating gate, erasing gate and control gate. The patterns of the control gates and the source regions in the memory cell array are arranged in parallel along the row direction of the memory cell array and the patterns of the erasing gates are arranged to extend in the column direction of the memory cell array. The memory cell transistors in the memory cell array are selected by a row decoder and a column decoder. An erasing circuit functions to erase memory data of each memory cell transistor by applying an erasing potential to the erasing gate of the memory cell transistor. A source potential generation circuit applies a first potential for programming and readout to the source region of a memory cell transistor selected by the row and column decoders when data is programmed into or read out from the selected memory cell transistor and applies a second potential which is higher than the first potential and lower than the erasing potential to the source region of each memory cell transistor when memory data of each memory cell transistor is erased by the erasing circuit. A potential difference between the source region and the erasing gate of the memory cell transistor in the erasing mode is reduced by the second potential output from the source potential generation circuit.