A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (36) for multiplying the input signal with a local oscillator signal (LO) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, additionally includes a circuit (30, 32) for directly generating a plurality of logic signals and a summer (34) for summing the logic signals to directly synthesize the local oscillator signal (LO). The local oscillator signal (LO) thereby produced has a fundamental component and third and fourth harmonic components and is shaped to ensure that each of the third and fourth harmonic components has an amplitude substantially less than that of the fundamental component. The disclosed circuit includes a reset mechanism (RESYNC) which quickly adjusts phase of the local oscillator signal (LO) by modifying the phase of the directly generated logic signals.