公开(公告)号：US6154460A

公开(公告)日：2000-11-28

申请号：US866884

申请日：1997-05-30

申请人： Daniel J. Kerns ,  Thomas A. Potter ,  Patrick K. Walp

发明人： Daniel J. Kerns ,  Thomas A. Potter ,  Patrick K. Walp

IPC分类号： H04L12/56

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9042

摘要： A data packet transmission system is disclosed. The system comprises a processor (178) having a memory block (202) and a communication controller (204). The processor (178) stores a data packet (205), a buffer descriptor array (206), and a header (208) in the memory block (202). The buffer descriptor array (206) has a first plurality of elements (206b, 206d, 206f, 206h, 206i), each indicating a respective segment (205a-205e) of the data packet (206), and a second plurality of elements (206a, 206c, 206e, 206g), each indicating the header (208). The processor (178) supplies the location of the buffer descriptor array (206) to the communication controller (204). In response, the communication controller (204) transmits a plurality of cells (222, 224, 226, 228), each cell including the header (208) and a segment of the data packet (205), to a destination system (180).

摘要翻译： 公开了一种数据分组传输系统。 该系统包括具有存储块（202）和通信控制器（204）的处理器（178）。 处理器（178）将数据分组（205），缓冲描述符阵列（206）和报头（208）存储在存储块（202）中。 缓冲描述符阵列（206）具有第一多个元素（206b，206d，206f，206h，206i），每个元素指示数据分组（206）的相应分段（205a-205e）和第二多个元素 206a，206c，206e，206g），每个指示标题（208）。 处理器（178）将缓冲器描述符阵列（206）的位置提供给通信控制器（204）。 作为响应，通信控制器（204）向目的地系统（180）发送包括报头（208）的每个小区和数据分组（205）的一部分的多个小区（222,224,226,228） 。

公开(公告)号：US4980648A

公开(公告)日：1990-12-25

申请号：US427152

申请日：1989-10-24

申请人： Kevin A. Jaeger ,  Patrick K. Walp

发明人： Kevin A. Jaeger ,  Patrick K. Walp

IPC分类号： H04L27/38

CPC分类号： H04L27/3818

摘要： A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (26) for multiplying the input signal with a local oscillator signal (LOa-LOd) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, operates in a SEARCH mode to supply acquisition reference signals (1xi, 1xq, 2xi, 2xq) to the multipliers (36). The resulting integrated values (Ia-Id) are proportional to the sine and cosine of the pahse (.phi.) of the input signal. The polarities (Sa-Sd) of these integrated values (Ia-Id) are processed to estimate this phase (.phi.) and to generate a reset signal (RESYNC) for the receiver (22) at the appropriate time.

摘要翻译： 一种具有用于接收用数字数据调制的输入信号的接口（24）的数字解调器或接收器（22），用于将输入信号与本地振荡器信号（LOa-LOd）相乘以产生乘积信号的乘法器（26） 以及用于周期性地积分乘积信号以产生每个具有指示数字数据的相应部分的幅度的积分信号序列的积分器（38），以SEARCH模式操作以提供采集参考信号（1xi，1xq，2xi ，2xq）耦合到乘法器（36）。 所得到的积分值（Ia-Id）与输入信号的pahse（phi）的正弦和余弦成比例。 处理这些积分值（Ia-Id）的极性（Sa-Sd）以估计该相位（phi），并在适当的时间产生用于接收器（22）的复位信号（RESYNC）。

公开(公告)号：US5826061A

公开(公告)日：1998-10-20

申请号：US660911

申请日：1996-06-10

申请人： Patrick K. Walp

发明人： Patrick K. Walp

IPC分类号： G06F7/58 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F7/588

摘要： A method for simulating the behavior of a metastable state machine is presented. The method includes outputting a transitional value when the state machine exhibits metastable behavior, such as when a set-up or hold violation occurs. A randomly-determined value is output after the transitional value is output for a predetermined period of time.

摘要翻译： 提出了一种用于模拟亚稳态机的行为的方法。 该方法包括当状态机显示亚稳态时输出过渡值，例如发生设置或保持违规时。 在过渡值输出预定时间段之后输出随机确定的值。

公开(公告)号：US4959844A

公开(公告)日：1990-09-25

申请号：US426367

申请日：1989-10-24

申请人： Patrick K. Walp

发明人： Patrick K. Walp

IPC分类号： H04L5/12 ,  H04L27/26 ,  H04L27/38

CPC分类号： H04L5/12 ,  H04L27/2657 ,  H04L27/3818

摘要： A digital demodulator (10) operates by multiplying an input signal with first and second orthogonal demodulation reference signals (Loa, LOb) to generate respective product signals, which are then integrated to generate first and second integrated values (a, b) indicative of digital data encoded in the input signal. These integrated values (a, b) are digitized to generate first and second digital values (a, b). A first error signal a-a) indicative of the difference between the first integrated value (a) and the first digital value (a) is generated, and the first error signal (a-a) is combined with the second digital value (b) to generate a first feedback signal. This first feedback signal is utilized to generate a control signal (ab-ba) indicative of phase difference between the input signal and the demodulation reference signals (LOa, LOb).

摘要翻译： 数字解调器（10）通过将输入信号与第一和第二正交解调参考信号（Loa，LOb）相乘来产生相应的乘积信号，然后被积分以产生指示数字的第一和第二积分值（a，b） 在输入信号中编码的数据。 这些积分值（a，b）被数字化以产生第一和第二数字值（â，b）。 产生指示第一积分值（a）和第一数字值（â）之间的差异的第一误差信号a-â），并且将第一误差信号（a-â）与第二数字值（b ）以产生第一反馈信号。 该第一反馈信号用于产生指示输入信号和解调参考信号（LOa，LOb）之间的相位差的控制信号（ab-b'）。

公开(公告)号：US5097487A

公开(公告)日：1992-03-17

申请号：US427281

申请日：1989-10-24

申请人： Patrick K. Walp

发明人： Patrick K. Walp

IPC分类号： H04L27/38

CPC分类号： H04L27/3836

摘要： A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (36) for multiplying the input signal with a local oscillator signal (LO) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, additionally includes a circuit (30, 32) for directly generating a plurality of logic signals and a summer (34) for summing the logic signals to directly synthesize the local oscillator signal (LO). The local oscillator signal (LO) thereby produced has a fundamental component and third and fourth harmonic components and is shaped to ensure that each of the third and fourth harmonic components has an amplitude substantially less than that of the fundamental component. The disclosed circuit includes a reset mechanism (RESYNC) which quickly adjusts phase of the local oscillator signal (LO) by modifying the phase of the directly generated logic signals.

摘要翻译： 一种具有用于接收用数字数据调制的输入信号的接口（24）的数字解调器或接收器（22），用于将输入信号与本地振荡器信号（LO）相乘以产生乘积信号的乘法器（36），以及 积分器（38），用于周期性地积分乘积信号以产生每个具有表示数字数据的相应部分的幅度的积分信号序列，另外包括用于直接生成多个逻辑信号的电路（30,32） 用于对逻辑信号求和以将本地振荡器信号（LO）直接合成的加法器（34）。 由此产生的本地振荡器信号（LO）具有基本分量和第三和第四谐波分量，并且被成形为确保第三和第四谐波分量中的每一个具有显着小于基波分量的幅度。 所公开的电路包括通过修改直接产生的逻辑信号的相位来快速调整本地振荡器信号（LO）的相位的复位机构（RESYNC）。

公开(公告)号：US4894797A

公开(公告)日：1990-01-16

申请号：US210147

申请日：1988-06-16

申请人： Patrick K. Walp

发明人： Patrick K. Walp

IPC分类号： G06F5/10

CPC分类号： G06F5/10

摘要： A first-in-first out (FIFO) register 100 for storage of up to two-bytes of data is operable by two control units 10, 20 for simultaneous read and write operations with no wait states. The FIFO register 100 comprises a first register 101, a second register 102 and a controller U35. The first register 101 may be multplexed between the two control units 10, 20 for write operations by either unit. The second register 102 is in communication with the first register 101 and may be read by either control unit 10, 20. Data is transferred from the first register 101 to the second register 102 under the direction of the controller U35 such that data may be read by one control unit 10, 20 while data is being simultaneously written by the other control unit 10, 20.

摘要翻译： 用于存储多达两字节数据的先进先出（FIFO）寄存器100可由两个控制单元10,20操作，用于不用等待状态的同时读和写操作。 FIFO寄存器100包括第一寄存器101，第二寄存器102和控制器U35。 第一寄存器101可以在两个控制单元10,20之间被多路复用，用于由任一单元进行写操作。 第二寄存器102与第一寄存器101通信，并且可以由控制单元10,20读取。数据在控制器U35的指导下从第一寄存器101传送到第二寄存器102，以便可以读取数据 同时由另一个控制单元10,20同时写入数据。

公开(公告)号：US4773082A

公开(公告)日：1988-09-20

申请号：US931576

申请日：1986-11-17

申请人： Gerald L. Somer ,  Patrick K. Walp

发明人： Gerald L. Somer ,  Patrick K. Walp

IPC分类号： H03H15/00 ,  H03H17/06 ,  H04B3/04 ,  H04L25/497 ,  H03K1/02 ,  G06F7/38

CPC分类号： H03H17/06 ,  H04L25/497

摘要： A binary transversal filter (200) in which the delay line of flip-flops (A-L, A'-L') is driven by timing signals (CLK, CLK*, CLKD, CLKD*) that are the same clock rate as the clock rate (CLK) of the encoded binary signals (IMPULSE 0, IMPULSE 1) being introduced into the delay line forming the binary transversal filters (200). The timing signal (CLK, CLK*, CLKD, CLKD*) that time or clock the stages of the delay line (A-L, A'-L') are phases of the clock (CLK) that introduces the encoded binary signals (IMPULSE 0, IMPULSE 1) into the delay line (A-L, A'-L'). Two substantially identical binary transversal filters (200a, 200b) are used to convert two encoded binary data streams (IMPULSE 0, IMPULSE 1) into a duobinary signal. The output of the two binary transversal filters (200a, 200b) are summed (Q2) and passed to a programmable amplifier (210), the gain of which is turned on when there is data in the encoded binary signals (IMPULSE 0, IMPULSE 1) to be converted and transmitted and is turned off otherwise. The carrier is prevented from being applied to the transmission medium (218) when the last bit of data in the encoded binary signals (IMPULSE 0, IMPULSE 1) has been converted to duobinary data by a binary transversal filter (200a, 200b) and applied to the medium (218). The encoded binary signal (IMPULSE 0, IMPULSE 1) inputted to the delay line (A-L, A'-L') of each binary transversal filter (200a, 200b) is monitored (25); the data shifted out of the last delay stage (L, L') of each binary transversal filter (200a, 200b) is also monitored (26). When the monitors (25, 26) indicated (27) that both encoded binary signals (IMPULSE 0, IMPULSE 1) are a logic 1 and the binary data shifted out of the last stage of delay (L, L') in both binary transversal filters (200a, 200b ) are also both logic 1, all meaningful data has been converted to duobinary data and transmitted on the medium (218) and therefore the carrier may be turned off.