A pipeline data processor includes an instruction fetch unit, an instruction decoding unit, an address calculation unit, an operand fetch unit and an instruction operation execution unit. After an instruction, or a part of an instruction, is sent from the instruction fetch unit to the decoding unit, the decoding unit decodes at least a portion of the instruction. For some instructions, the decoding unit outputs two or more step codes to achieve processing of a single operand address. In one embodiment, the operand specifier of the instruction includes a base value and at least one address extension field. The decoding unit outputs a first step code based on the base value and, subsequently, a second step code based on the address extension field. In another embodiment, an operand specifier can include up to an arbitrary number of address extension fields. The decoding unit outputs a step code corresponding to the base value of the address and another step code for each of the plurality of address extension fields. The address calculation unit sequentially receives the plurality of step codes which relate to a single operand and, when address calculation of the operand is completed, sends the result as a fuuther step code to the operand fetch unit.