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    Atomic operation predictor to predict whether an atomic operation will complete successfully
    1.
    发明授权
    Atomic operation predictor to predict whether an atomic operation will complete successfully 有权

    公开(公告)号：US12229557B2

    公开(公告)日：2025-02-18

    申请号：US18601640

    申请日：2024-03-11

    Applicant: Apple Inc.

    Inventor： Brian R. Mestan ,  Gideon N. Levinsky ,  Michael L. Karm

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/52

    Abstract: In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.

    Monitoring performance cost of events
    2.
    发明授权
    Monitoring performance cost of events 有权

    公开(公告)号：US12204430B2

    公开(公告)日：2025-01-21

    申请号：US17033746

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin

    IPC: G06F1/30 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

    Abstract: Embodiments are disclosed for monitoring processor performance, including cost of events. In an embodiment, a processor includes a first counter, a second counter, a handler circuit, and an enable circuit. The first counter is to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value. The second counter to measure a performance cost of the event. The handler circuit to generate and an event sampling record. The record is to include at least one value reflecting the performance cost. The enable circuit is to enable the handler circuit to generate the record.

    POLARITY-BASED DATA PREFETCHER WITH UNDERLYING STRIDE DETECTION
    3.
    发明申请
    POLARITY-BASED DATA PREFETCHER WITH UNDERLYING STRIDE DETECTION 有权

    公开(公告)号：US20250021336A1

    公开(公告)日：2025-01-16

    申请号：US18768088

    申请日：2024-07-10

    Applicant: Akeana, Inc.

    Inventor： Rabin Sugumar

    IPC: G06F9/38 ,  G06F9/32

    Abstract: A processor core includes a local cache hierarchy, prefetch logic, and a prefetch table, where the processor core is coupled to an external memory system. A data stream is detected, where the data stream includes multiple load instructions, including a load instruction that causes a cache miss, resulting in prefetching. A prefetch table is initialized with information pertaining to load instructions, and includes a Positive or Negative value (PON), a stride, and a saturation count. Information in the prefetch table is updated as new load instructions are prefetched. An underlying stride of the data stream is discovered, based on the updating. Data is prefetched using an offset, where a polarity of the offset is based on the PON, enabling effective stride detection with dynamic directionality and out-of-order instructions.

    INSTRUCTION TRANSLATION METHOD AND RELATED DEVICE THEREOF
    4.
    发明申请
    INSTRUCTION TRANSLATION METHOD AND RELATED DEVICE THEREOF 有权

    公开(公告)号：US20250013468A1

    公开(公告)日：2025-01-09

    申请号：US18898309

    申请日：2024-09-26

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Xianzhe LIU ,  Jianjiang ZENG ,  Yandong LV

    IPC: G06F9/30 ,  G06F9/32

    Abstract: Embodiments of this application disclose an instruction translation method. The method includes: obtaining a return instruction of a function call instruction; obtaining a first address mapping result based on a second address indicated in the return instruction; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction, where the first translation result is a binary translation result of the return instruction, and the second translation result indicates to obtain, from a target location, an instruction indicated by the first address mapping result and execute the instruction. In this application, a running stack space of a source program is reused, thereby saving a storage space. In addition, an address of a return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation and increasing program running efficiency.

    SECURE PROCESSOR FOR DETECTING AND PREVENTING EXPLOITS OF SOFTWARE VULNERABILITY
    7.
    发明申请
    SECURE PROCESSOR FOR DETECTING AND PREVENTING EXPLOITS OF SOFTWARE VULNERABILITY 有权

    公开(公告)号：US20240403394A1

    公开(公告)日：2024-12-05

    申请号：US18801580

    申请日：2024-08-12

    Applicant: The Research Foundation for The State University of New York

    Inventor： Kanad Ghose

    IPC: G06F21/12 ,  G06F9/32 ,  G06F9/38 ,  G06F12/10 ,  G06F21/62

    Abstract: A secure processor, comprising a logic execution unit configured to process data based on instructions; a communication interface unit, configured to transfer of the instructions and the data, and metadata tags accompanying respective instructions and data; a metadata processing unit, configured to enforce specific restrictions with respect to at least execution of instructions, access to resources, and manipulation of data, selectively dependent on the received metadata tags; and a control transfer processing unit, configured to validate a branch instruction execution and an entry point instruction of each control transfer, selectively dependent on the respective metadata tags.

    Mixed scalar and vector operations in multi-threaded computing
    9.
    发明授权
    Mixed scalar and vector operations in multi-threaded computing 有权

    公开(公告)号：US12131157B2

    公开(公告)日：2024-10-29

    申请号：US17984336

    申请日：2022-11-10

    Applicant: AzurEngine Technologies Zhuhai Inc.

    Inventor： Toshio Nagata ,  Yuan Li ,  Jianbin Zhu ,  Ryan Braidwood

    IPC: G06F9/30 ,  G06F9/32

    CPC classification number: G06F9/30145 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/321

    Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer configured to: decode instructions that include scalar instructions and vector instructions, execute decoded scalar instructions, and package decoded vector instructions as configurations. The processor may further include a plurality of columns of vector processing units coupled to the sequencer. The plurality of columns of vector processing units may include a plurality of processing elements (PEs) and each of the PEs may include a plurality of Arithmetic Logic Units (ALUs). The sequencer may be configured to send the configurations to the plurality of columns of vector processing units.

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