发明授权
US5133064A Data processing system generating clock signal from an input clock,
phase locked to the input clock and used for clocking logic devices
失效
数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
- 专利标题： Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
- 专利标题（中）： 数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
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申请号： US184782申请日： 1988-04-22
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公开(公告)号： US5133064A公开(公告)日： 1992-07-21
- 发明人: Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
- 申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX62-101930 19870427; JPX62-181060 19870722
- 主分类号： G06F1/10
- IPC分类号： G06F1/10 ; H03K5/156 ; H03L7/18
摘要：
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
公开/授权文献
- US6092087A Log file optimization in a client/server computing system 公开/授权日：2000-07-18
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