公开(公告)号：US07424598B2

公开(公告)日：2008-09-09

申请号：US09853769

申请日：2001-05-14

Applicant: Takashi Hotta ,  Shigeya Tanaka ,  Hideo Maejima

Inventor： Takashi Hotta ,  Shigeya Tanaka ,  Hideo Maejima

IPC: G06F9/30 ,  G06F9/302

CPC classification number: G06F9/3889 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

Abstract: The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Abstract translation: 用于由管线系统执行由有线逻辑实现的指令的数据处理器包括多个指令寄存器和相同数量的算术运算单元。 一次在一个机器周期中在指令寄存器中读取的多个指令由多个算术运算单元并行处理。

公开(公告)号：US06760832B2

公开(公告)日：2004-07-06

申请号：US10281148

申请日：2002-10-28

Applicant: Junichi Nishimoto ,  Hideo Maejima

Inventor： Junichi Nishimoto ,  Hideo Maejima

IPC: G06F922

CPC classification number: G06F9/3822 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract translation: 一种数据处理器，包括用于执行第一指令集的第一处理器和用于执行不同于第一指令集的第二指令集的第二处理器。 当第一处理器执行第一指令集的预定指令时，第二处理器执行第二指令集的指令。 第一处理器可以是精简指令集计算机（RISC）型处理器，第二处理器可以是非常长的指令字（VLIW）型处理器，第一指令集可以是RISC指令集，第二指令集可以是 VLIW指令集。 由第一处理器执行的RISC指令集的预定指令可以是使分支指向存储VLIW指令的特定地址空间的分支指令。 此后，VLIW型处理器执行特定地址空间处的VLIW指令。

公开(公告)号：US5638095A

公开(公告)日：1997-06-10

申请号：US430848

申请日：1995-04-28

Applicant: Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

Inventor： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399

CPC classification number: G09G5/395 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G06T17/00 ,  G09G5/024 ,  G09G5/20 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/127 ,  G09G5/36

Abstract: A graphic pattern processing apparatus having a display memory, a data processor, a graphic processor, and a plurality of parallel to serial convertors. The display memory stores graphic data in words, each word has a plurality of pixel data and each pixel data has a plurality of bits. A graphic processor accesses the display memory and processes a plurality of the pixel data in response to instructions received from a data processor. The number of parallel to serial convertors corresponds to the number of bits per pixel and are configured to allow a word from the display memory to be converted into a serial stream of pixel data.

Abstract translation: 具有显示存储器，数据处理器，图形处理器和多个并行到串行转换器的图形处理装置。 显示存储器以单词存储图形数据，每个单词具有多个像素数据，并且每个像素数据具有多个位。 图形处理器响应于从数据处理器接收到的指令，访问显示存储器并处理多个像素数据。 并行到串行转换器的数量对应于每像素的位数，并且被配置为允许来自显示存储器的字被转换成像素数据的串行流。

公开(公告)号：US5506982A

公开(公告)日：1996-04-09

申请号：US278245

申请日：1994-07-21

Applicant: Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

Inventor： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC: G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/06

CPC classification number: H03K5/1565 ,  G06F1/10 ,  H03L7/18

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

公开(公告)号：US5485407A

公开(公告)日：1996-01-16

申请号：US152390

申请日：1993-11-16

Applicant: Shigeru Ishimoto ,  Yasuhiko Matuyama ,  Hideo Maejima

Inventor： Shigeru Ishimoto ,  Yasuhiko Matuyama ,  Hideo Maejima

IPC: G01D5/245 ,  G01D5/244 ,  G06G7/30

CPC classification number: G01D5/24476 ,  G01D5/2448

Abstract: An interpolation device for a scale arrangement receives sine wave and cosine wave signals indicative of a measuring data from the scale arrangement and calculates a DC offset value, an amplitude coefficient and an amount of a phase drift on the basis of the received signals. The interpolation device outputs a correct angle signal upon removing a DC offset, a gain level error, a gain unbalance and a phase drift from received signals. Therefore, the interpolation device realizes a mechanical structure of the scale arrangement to be simple.

Abstract translation: 用于刻度布置的内插装置接收指示来自刻度装置的测量数据的正弦波和余弦波信号，并且基于接收的信号计算DC偏移值，幅度系数和相位漂移量。 在从接收到的信号中去除DC偏移，增益电平误差，增益不平衡和相位漂移时，内插装置输出正确的角度信号。 因此，插值装置实现了刻度装置的机械结构简单。

公开(公告)号：US5432443A

公开(公告)日：1995-07-11

申请号：US79569

申请日：1993-06-22

Applicant: Hideo Maejima ,  Motokazu Kamiyama

Inventor： Hideo Maejima ,  Motokazu Kamiyama

IPC: G01D5/14 ,  G01D5/245 ,  G01B7/02 ,  G01B11/02

CPC classification number: G01D5/145 ,  G01D5/2451

Abstract: An apparatus for detecting a relative displacement between a scale and a head is disclosed in which an equilibrium modulated signal derived from at least one detecting head is processed and converted into a DC voltage signal, a level of the DC voltage signal indicating the relative displacement of the scale to the head. At least one sample-and-hold circuit (its sampling time is synchronized with a reference signal, i.e., an excitation signal supplied to the head) or peak/hold circuit and low-pass filter (smoother) is used to provide the DC voltage signal.

Abstract translation: 公开了一种用于检测标尺和头部之间的相对位移的装置，其中从至少一个检测头导出的平衡调制信号被处理并转换为直流电压信号，指示相对位移的直流电压信号的电平 规模到头。 使用至少一个采样保持电路（其采样时间与参考信号同步，即提供给磁头的激励信号）或峰值/保持电路和低通滤波器（更平滑）来提供直流电压 信号。

公开(公告)号：US5430397A

公开(公告)日：1995-07-04

申请号：US186544

申请日：1994-01-26

Applicant: Hiroyuki Itoh ,  Noboru Masuda ,  Hideo Maejima ,  Tadahiko Nishimukai

Inventor： Hiroyuki Itoh ,  Noboru Masuda ,  Hideo Maejima ,  Tadahiko Nishimukai

IPC: G06F1/10 ,  H03K5/15 ,  H03K19/00 ,  H03K5/00

CPC classification number: G06F1/10 ,  H03K5/1506

Abstract: An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.

Abstract translation: 一种LSI内部时钟分配电路，包括主分配电路，多个块内时钟分配电路，与每个块相关联地设置的每个连接到相关块内的多个基于块的时钟信号线中的一个的反馈线 以及相关联的块的块内分布电路，用于将分配到连接到块内时钟信号线的给定一个电路元件的块内时钟信号反馈到该块的块内时钟分配电路。 每个块中的块内时钟分配电路通过经连接到其的基于块的时钟信号线之一和通过反馈线反馈的块内时钟信号来响应提供给相关块的块目的地时钟信号 从而产生具有取决于块目的地时钟信号和反馈块内时钟信号之间的相位差的各个相位的多个块内时钟信号。

公开(公告)号：US5332995A

公开(公告)日：1994-07-26

申请号：US736780

申请日：1991-07-29

Applicant: Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

Inventor： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G5/38

CPC classification number: G09G5/395 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G06T17/00 ,  G09G5/024 ,  G09G5/20 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/127 ,  G09G5/36

Abstract: A graphic data generating apparatus includes an output producing a graphic image having a plurality of bits; a display memory connected to the output for storing pixel data defining the graphic data for each of the pixel data having a plurality of bits; and a graphic data processing apparatus performing read out of word data having a plurality of pixel data at a word position of the display memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the display memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

Abstract translation: 图形数据生成装置包括产生具有多个位的图形图像的输出; 连接到输出端的显示存储器，用于存储定义用于具有多个位的每个像素数据的图形数据的像素数据; 以及图形数据处理装置，执行在由源存储器地址指定的显示存储器的字位置处读出具有多个像素数据的字数据，选择由读出字中的源像素地址指定的像素数据，并写入所选择的 在由目的地存储器地址指定的字数据的目的地像素地址指定的像素位置处的显示存储器中的像素数据。

公开(公告)号：US4954943A

公开(公告)日：1990-09-04

申请号：US415722

申请日：1989-10-02

Applicant: Ikuya Kawasaki ,  Keiichi Kurakazu ,  Hideo Maejima

Inventor： Ikuya Kawasaki ,  Keiichi Kurakazu ,  Hideo Maejima

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F9/3822 ,  G06F9/30149 ,  G06F9/3824

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

公开(公告)号：US4779210A

公开(公告)日：1988-10-18

申请号：US727850

申请日：1985-04-26

Applicant: Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

Inventor： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/36 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G06F15/20 ,  G06F3/153

CPC classification number: G06T17/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G09G5/36

Abstract: Herein disclosed is a graphic processing apparatus which uses a CRT of raster scanning type. The graphic processing apparatus has functions to compare and judge whether or not within the range of a predetermined region thereby to effect the drawing operation, to compare drawing picture element data and other data in the drawing operation thereby to arithmetically control the drawing picture element data in accordance with the compared result, and to drawing a pattern of an arbitrary size on the basis of a fundamental unit of line and design patterns in the drawing operation.

Abstract translation: 这里公开了使用光栅扫描型CRT的图形处理装置。 图形处理装置具有比较判定是否在预定区域的范围内进行绘图操作的功能，以便在绘图操作中比较绘制图像元素数据和其他数据，从而对图形元素数据进行算术控制 根据比较结果，并在绘图操作中基于线和设计图案的基本单位绘制任意尺寸的图案。