发明授权
- 专利标题: Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the source/drain regions
- 专利标题(中): 通过控制源/漏区域中P型污染物密度的简档来制造半导体器件的方法
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申请号: US666912申请日: 1991-03-11
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公开(公告)号: US5147811A公开(公告)日: 1992-09-15
- 发明人: Eiji Sakagami
- 申请人: Eiji Sakagami
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX2-61531 19900313
- 主分类号: H01L21/265
- IPC分类号: H01L21/265 ; H01L21/336 ; H01L27/115 ; H01L29/08 ; H01L29/10
摘要:
The invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following, formation of a floating gate electrode on a region predetermined for the formation of the first conductive channel across an insulation film, followed by superimposition of a control gate electrode on the floating gate electrode across another insulation film. After completing the formation of the stacked gate electrode unit, the first conductive impurities are injected into silicon substrate by applying a minimum of 8 degrees of angle against the normal of this substrate under aid of ionic injection, and then forms a region containing strong density of the first conductive impurities adjacent to the boundary of a layer of diffused second conductive impurities which is at least predetermined to become the drain region of the transistor incorporating the stacked gate electrode unit. As a result of the provision of the region containing strong density of impurities injected in the oblique direction, the efficiency in the writing of data into the floating gate electrode is significantly promoted, and at the same time occurrence of "short-channel" effect can securely be suppressed as well.
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