A frequency synthesizer circuit (10). Circuit (10) has a counter (12), a latch/decoder (14), a divider (16), and an optional wave shaper (18) which synthesize an output clock signal X. Counter (12) counts a number of clock signal N periods that occur within one clock signal M period and this count is stored as a count value. The count value is latched and/or decoded by the latch/decoder (14) to produce a divisor which is output from the latch/decoder (14) to the divider (16). The divider (16) divides a clock signal N frequency by the divisor to provide a spiked waveform to the wave shaper (18). The wave shaper (18) alters a frequency and/or a duty cycle of the spiked waveform to produce the clock signal X. Clock signal X has a substantially constant frequency regardless of the clock signal N frequency or operational variation in the system clock N frequency.