发明授权
US5175826A Delayed cache write enable circuit for a dual bus microcomputer system
with an 80386 and 82385
失效
具有80386和82385的双总线微型计算机系统延迟缓存写入电路
- 专利标题： Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
- 专利标题（中）： 具有80386和82385的双总线微型计算机系统延迟缓存写入电路
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申请号： US198890申请日： 1988-05-26
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公开(公告)号： US5175826A公开(公告)日： 1992-12-29
- 发明人: Ralph M. Begun , Patrick M. Bland , Mark E. Dean
- 申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
- 申请人地址： NY Armonk
- 专利权人： IBM Corporation
- 当前专利权人： IBM Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F12/08
- IPC分类号： G06F12/08
摘要：
In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.
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