发明授权
- 专利标题： Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement
- 专利标题（中）： 半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列
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申请号： US821875申请日： 1992-01-16
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公开(公告)号： US5184321A公开(公告)日： 1993-02-02
- 发明人: Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
- 申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX63-309242 19881206
- 主分类号： G11C11/4074
- IPC分类号： G11C11/4074 ; G11C11/408
摘要：
A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.