公开(公告)号：US06170036A

公开(公告)日：2001-01-02

申请号：US08780066

申请日：1996-12-23

申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC分类号： G06F1300

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

摘要： A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

摘要翻译： 半导体存储器件被配置为包括静态随机存取存储器（SRAM）阵列和动态随机存取存储器（DRAM）阵列。 存储器件包括内部数据线，其能够在SRAM和DRAM阵列之间传输数据块。 数据传输电路与内部数据线分开提供，并且包括用于锁存要传送的数据的锁存电路。 数据传输电路响应传输指定信号。

公开(公告)号：US6026029A

公开(公告)日：2000-02-15

申请号：US865310

申请日：1997-05-29

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5848004A

公开(公告)日：1998-12-08

申请号：US625578

申请日：1996-03-28

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5777942A

公开(公告)日：1998-07-07

申请号：US149680

申请日：1993-11-08

申请人： Katsumi Dosaka ,  Toshiyuki Omoto ,  Masaki Kumanoya

发明人： Katsumi Dosaka ,  Toshiyuki Omoto ,  Masaki Kumanoya

IPC分类号： G06F12/08 ,  G11C11/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  G11C8/00

CPC分类号： G06F12/0893 ,  G11C11/005

摘要： A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

公开(公告)号：US5603009A

公开(公告)日：1997-02-11

申请号：US356046

申请日：1994-12-14

申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G06F13/00 ,  G11C11/34

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C11/005 ,  G11C7/103 ,  G11C7/1045 ,  G11C2207/2254

摘要： A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.

摘要翻译： 包含高速缓存的半导体存储器件包括作为高速缓冲存储器的静态随机存取存储器（SRAM）和作为主存储器的动态随机存取存储器（DRAM）。 通过双向数据传输门电路和内部数据线，可以在DRAM和SRAM之间进行数据块的集中传输。 在DRAM中提供DRAM行解码器和DRAM列解码器。 在SRAM中提供SRAM行解码器和SRAM列解码器。 SRAM和DRAM的地址可以独立应用。 数据传输门包括一个锁存电路，用于锁存来自用作高速存储器的SRAM的数据，放大器电路和用于放大来自DRAM的数据的门电路，其用作大容量存储器，并用于发送放大 数据到SRAM，以及门电路，响应于用于将写入数据发送到DRAM的相应存储器单元的DRAM写使能信号。 在SRAM的数据被锁存电路锁存之后，写入数据从门电路传输到DRAM，写数据通过放大电路和门电路传输到SRAM。

公开(公告)号：US5151614A

公开(公告)日：1992-09-29

申请号：US725037

申请日：1991-07-03

申请人： Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

发明人： Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K3/356 ,  H03K17/22

CPC分类号： H03K3/356008 ,  H03K17/223 ,  H01L2924/0002

摘要： A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor. This turns on the transistor near the node, so that the residual charges in the node are offset by the negative charges in the connection point.

摘要翻译： 公开了一种连接到上电复位脉冲发生电路中的节点的剩余电荷去除电路，用于去除当电源关闭时保留在该节点中的正电荷。 该剩余电荷去除电路由串联在节点和地之间的两个N沟道MOS晶体管和一个电容器组成。 在两个N沟道MOS晶体管中，节点附近的晶体管具有接地栅极。 电容器连接在离节点的两个N沟道MOS晶体管中的晶体管的栅极和电源之间。 远离节点的晶体管的栅极连接到两个N沟道MOS晶体管之间的连接点。 因此，当电源电压由于断电而降低到MOS晶体管的阈值电压Vth以下时，远离节点的晶体管截止，使得由于放电为负的连接点的电位变为-Vth 从电容器充电。 这使得节点附近的晶体管导通，使得节点中的剩余电荷被连接点中的负电荷抵消。

公开(公告)号：US5097440A

公开(公告)日：1992-03-17

申请号：US437867

申请日：1989-11-17

申请人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

发明人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC分类号： G11C11/401 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

摘要翻译： 半导体存储器件包括布置在一列中的八个存储器阵列（b 10a，10b）。 外围电路（60）布置在八个存储器阵列（10a，10b）的中心部分中，两个列解码器（51,52）被布置在外围电路（60）之间。 八个存储器阵列（10a，10b）中的每一个都具有行解码器（20）。 多列第一列选择线（CL1）被设置为跨越从列解码器（51）排列在外围电路（60）一侧的三个存储器阵列（10a，10b）。 另外，多列第二列选择线（CL2）被设置成与从列解码器（52）配置在外围电路（60）的另一侧的三个存储器阵列（10a，10b）相交。

公开(公告)号：US4896297A

公开(公告)日：1990-01-23

申请号：US112034

申请日：1987-10-23

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

摘要翻译： 一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于 当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

公开(公告)号：US4760559A

公开(公告)日：1988-07-26

申请号：US883311

申请日：1986-07-08

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/4085

摘要： A dynamic type MOS-RAM constructed of folded type bit lines and having sense operation cycles for amplifying potential difference appearing on respective pairs of bit lines after selection of a word line and restore operation cycles for further amplifying the potential difference on the pairs of bit lines after the sense operation cycles, wherein non-selected word lines are completely brought into electrically floating states in intervals including the sense operation cycles and the restore operation cycles.

摘要翻译： 由折叠型位线构成的具有读出操作周期的动态型MOS-RAM，用于放大在选择字线之后出现在各对位线上的电位差，并且还原操作周期用于进一步放大位线对上的电位差 在感测操作周期之后，其中未选择的字线在包括感测操作周期和恢复操作周期的间隔中完全进入电浮动状态。

公开(公告)号：US4692901A

公开(公告)日：1987-09-08

申请号：US762632

申请日：1985-08-05

申请人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

发明人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

IPC分类号： G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

摘要翻译： 半导体存储器包括存储单元（15-18,27-30），数据写入端（1），数据读出端（48），晶体管（3-10,35-42），地址信号输入端（23- 26），子代码信号输入端子（43-46），驱动信号发生电路（49-52），并行读出电路（79-82）和测试模式切换信号输入端子（53,88）。 在写入存储单元的功能测试数据时，驱动信号发生电路响应于测试模式切换信号而使所有晶体管（3-10）响应于地址信号，从而同时将数据写入存储器 细胞（15-18）。 此外，在读出存储单元的功能测试数据时，并行读出电路响应于不考虑子代码信号的测试模式切换信号读取存储测试数据的存储单元（27-30）的存储内容。 可以提供逻辑电路装置（90,91,94）以当测试数据的所有逻辑值处于相同电平时输出与存储在存储单元中的测试数据相对应的逻辑值。