发明授权
- 专利标题: Information processing system having power saving control of the processor clock
- 专利标题(中): 具有处理器时钟功率控制的信息处理系统
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申请号: US840417申请日: 1992-02-24
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公开(公告)号: US5189647A公开(公告)日: 1993-02-23
- 发明人: Naoshi Suzuki , Shunya Uno
- 申请人: Naoshi Suzuki , Shunya Uno
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corp.
- 当前专利权人: International Business Machines Corp.
- 当前专利权人地址: NY Armonk
- 优先权: JPX3-050307 19910225
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/08 ; G06F1/32 ; G06F9/48
摘要:
An information processing system operates under a multi-tasking operating system in which each task to be run is assigned a priority level. A Clock Switch (41) is positioned between the Clock Oscillator (50) and the Processor (10). A System Timer (70) establishes periodic intervals of time. At the beginning of each time interval, the System Timer, via an Interrupt Controller (60) and Transition Detector (42), turns ON (if its not already ON) the clock to the Processor by sending a Clock Start Signal to the Clock Switch. A Clock Control Program is assigned the lowest priority such that the Clock Control Program runs if and only if there are no other tasks running. When the Clock Control Program runs, it sends a code to a Register (43), which in turn sends a Clock Stop signal to the Clock Switch, thereby stopping the clock to the Processor. As described above, the System Timer will restart the clock again at the beginning of the next time interval. By stopping the clock to the Processor, the power to and the heat dissipated by the Processor are reduced. In an alternate embodiment, the frequency of the clock signal to the processor is reduced, rather than completely stopping the clock to the Processor.
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