发明授权
- 专利标题: Programmable interconnect architecture
- 专利标题(中): 可编程互连体系结构
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申请号: US899729申请日: 1992-06-17
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公开(公告)号: US5191241A公开(公告)日: 1993-03-02
- 发明人: John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
- 申请人: John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
- 申请人地址: CA Sunnyvale
- 专利权人: Actel Corporation
- 当前专利权人: Actel Corporation
- 当前专利权人地址: CA Sunnyvale
- 主分类号: H01L23/525
- IPC分类号: H01L23/525 ; H01L23/528
摘要:
A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
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