-
公开(公告)号：US5191241A
公开(公告)日：1993-03-02
申请号：US899729
申请日：1992-06-17
IPC分类号： H01L23/525 , H01L23/528
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
摘要翻译： 用户可配置电路架构包括布置在半导体衬底内的功能电路模块的二维阵列。 设置在半导体衬底上方并与半导体衬底绝缘的第一互连层包含多个导体并且用于功能电路模块内的内部连接。 设置在第一互连层之上并与第一互连层绝缘的第二互连层包含沿第一方向运行的多个导体的导体轨道，并用于互连功能电路模块的输入和输出。 设置在第二互连层之上并与第二互连层绝缘的第三互连层包含沿第二方向延伸的导体的多个分段轨迹，导体中的一些导体与第二互连层中的导体中的一个段形成相交;以及 用于互连功能电路模块输入和输出以实现所需的应用。 多个用户可配置的互连元件直接放置在第二和第三互连层中的分段导体的选定段的交叉处的第二和第三互连层之间。 更多用户可配置的互连元件位于第二和第三互连层中的分段导体的相邻段之间。 位于功能电路模块之间的半导体衬底中的通过晶体管连接在第二和第三互连层中的相邻段之间以及第二和第三互连层中的选定交叉段之间。
-
2.发明授权Programmable interconnect architecture having interconnects disposed above function modules 失效具有处于上述功能模块的互连的可编程互连架构
公开(公告)号：US5132571A
公开(公告)日：1992-07-21
申请号：US561110
申请日：1990-08-01
IPC分类号： H01L21/82 , H01L23/525 , H01L23/528 , H03K19/177
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second the third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
-
公开(公告)号：US4873459A
公开(公告)日：1989-10-10
申请号：US195728
申请日：1988-05-18
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17748 , G01R31/318516 , H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/17796
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segements connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conducive to custom circuit design.
摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 布线通道包括通过常开的可编程元件连接的布线段，位于要连接的任何两个段的交点处。 可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。 通用功能模块可以被配置为实现流行的逻辑功能并且具有有利于定制电路设计的物理布局。
-
公开(公告)号：US07932744B1
公开(公告)日：2011-04-26
申请号：US12142118
申请日：2008-06-19
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.
摘要翻译： 集成电路的I / O方案包括组布局单元。 组布局单元包括多个信号I / O焊盘。 驱动器电路耦合到每个信号I / O焊盘。 组布局单元还包括两个I / O驱动器电路电源板。 ESD保护电路耦合到多个驱动器电路。 信号I / O焊盘和I / O驱动器电路电源板排列成行。 行可以是规则的或交错的。
-
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是 连接开关可耦合到多个位线B中的一个，每个位线与列相关联。
-
公开(公告)号：US5440245A
公开(公告)日：1995-08-08
申请号：US028789
申请日：1993-03-09
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs. The output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output is and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer. The select input of the fifth two-input multiplexer is connected to a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth two-input multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data signal of one of the other groups.
摘要翻译： 逻辑模块包括第一和第二双输入多路复用器，每个具有第一和第二数据输入。 第一和第二多路复用器都包括选择输入，它们都连接到具有第一和第二数据输入的具有第一类型的双输入逻辑门的输出。 对第一和第二双输入多路复用器的输入来自第一组的数据信号。 每个逻辑门的一个输入源自第二组的数据信号，并且每个逻辑门的另一个输入源自第三组的数据信号。 第三双输入多路复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入。 第三双输入多路复用器的选择输入连接到具有第一和第二数据输入的具有第二类型的两输入逻辑门的输出。 第三双输入多路复用器的输出连接到具有耦合到其选择输入的HOLD1输入的第四双输入多路复用器的第一数据输入。 其输出为CLEAR输入，并将其输出连接到第四个双输入多路复用器的第二数据输入端和第五个双输入多路复用器的第一个数据输入端的与门。 第五个双输入多路复用器的选择输入连接到一个HOLD2输入。 其输出和CLEAR输入被呈现给AND门，其输出端连接到第五个双输入多路复用器的第二个数据输入端和一个输出节点。 CLEAR，HOLD1和HOLD2输入由来自第三组的数据信号的组合组成，其可以包含其他组中的一个的数据信号。
-
公开(公告)号：US20100315118A1
公开(公告)日：2010-12-16
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是 连接开关可耦合到多个位线B中的一个，每个位线与列相关联。
-
公开(公告)号：US07816946B1
公开(公告)日：2010-10-19
申请号：US12360948
申请日：2009-01-28
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译： 公开了一种用于现场可编程门阵列集成电路器件的触发器。 触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号 时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。
-
公开(公告)号：US5781033A
公开(公告)日：1998-07-14
申请号：US754188
申请日：1996-11-12
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.
摘要翻译： 逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。 两个选择输入都连接到第一类型的双输入逻辑门的输出。 第一和第二多路复用器的输入包括来自第一组的数据信号。 每个逻辑门的一个输入包括第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。 第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。 其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。 其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。 第五多路复用器选择输入包括一个HOLD2输入。 其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。
-
公开(公告)号：US5055718A
公开(公告)日：1991-10-08
申请号：US522232
申请日：1990-05-11
IPC分类号： G06F17/10 , H03K3/037 , H03K19/173
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two-input logic gate of a second type having first and second data inputs.The output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output is and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer. The select input of the fifth two-input multiplexer is connected to a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth two-input multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data siganl of one of the other groups.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.023 秒)
